公开(公告)号：US20120099382A1

公开(公告)日：2012-04-26

申请号：US12908670

申请日：2010-10-20

Applicant: Jui-Jen WU ,  Shao-Yu CHOU

Inventor： Jui-Jen WU ,  Shao-Yu CHOU

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C7/04 ,  G11C7/12 ,  G11C7/14 ,  G11C11/412 ,  G11C11/413

Abstract: A circuit includes a reference data line configured to receive a reference voltage value, a memory cell, a data line coupled to the memory cell and configured to have a data logic value associated with data stored in the memory cell, a first circuit coupled to the reference data line and to the data line, and an output node configured to selectively receive the data logic value from the data line or receive the data logic value through the first circuit, based on the reference voltage value and a trip point used to trigger the first circuit to provide the data logic value through the first circuit.

Abstract translation: 电路包括被配置为接收参考电压值的参考数据线，存储器单元，耦合到存储器单元的数据线，并被配置为具有与存储在存储单元中的数据相关联的数据逻辑值，第一电路耦合到 参考数据线和数据线，以及输出节点，被配置为基于参考电压值和用于触发数据逻辑值的触发点，从数据线选择性地接收数据逻辑值或通过第一电路接收数据逻辑值 第一电路通过第一电路提供数据逻辑值。

公开(公告)号：US20110235448A1

公开(公告)日：2011-09-29

申请号：US12732931

申请日：2010-03-26

Applicant: Jui-Jen WU

Inventor： Jui-Jen WU

IPC: G11C7/00 ,  G11C7/06

CPC classification number: G11C7/12 ,  G11C7/08 ,  G11C7/18 ,  G11C8/14 ,  G11C11/413 ,  G11C2207/002 ,  G11C2207/005

Abstract: In some embodiments related to reading data in a memory cell, the data is driven to a local bit line, which drives a local sense amplifier. Depending on the logic level of the data in the memory cell and thus the local bit line, the local sense amplifier transfers the data on the local bit line to a global bit line. A neighbor global bit line is used as a reference for a global sense amplifier to read the differential data on the global bit line and the neighbor global bit line.

Abstract translation: 在与存储器单元中读取数据相关的一些实施例中，数据被驱动到驱动局部读出放大器的局部位线。 根据存储器单元中的数据的逻辑电平以及局部位线，局部读出放大器将局部位线上的数据传送到全局位线。 相邻全局位线用作全局读出放大器的参考，以读取全局位线和邻近全局位线上的差分数据。

公开(公告)号：US20140043886A1

公开(公告)日：2014-02-13

申请号：US13570305

申请日：2012-08-09

Applicant: Jui-Jen WU ,  Meng-Fan CHANG

Inventor： Jui-Jen WU ,  Meng-Fan CHANG

IPC: G11C7/10 ,  G11C7/12 ,  G11C11/21

CPC classification number: G11C7/12 ,  G11C7/065 ,  G11C7/14 ,  G11C11/419

Abstract: A digital memory element has a sense circuit latch to read the value stored in a bit cell. Before addressing a word line, the bit lines are precharged. During the read operation, a bit line is coupled to a supply voltage through a bit cell memory element that has different resistances at logic states “0” and “1.” A reference bit line is coupled to the supply voltage through a comparison resistance value, especially a resistance between high and low resistance of the memory element in the two logic states. Voltages on the bit line and reference bit line ramp toward a switching threshold at rates related to the resistance values. The first line to discharge to switching threshold voltage sets the sense circuit latch.

Abstract translation: 数字存储元件具有用于读取存储在位单元中的值的读出电路锁存器。 在寻址字线之前，位线是预先充电的。 在读取操作期间，位线通过在逻辑状态“0”和“1”处具有不同电阻的位单元存储元件耦合到电源电压。 参考位线通过比较电阻值耦合到电源电压，特别是两个逻辑状态下存储元件的高电阻和低电阻之间的电阻。 在与电阻值相关的速率下，位线上的电压和参考位线斜坡转向切换阈值。 第一行放电到开关阈值电压设置感测电路锁存器。

公开(公告)号：US20120051151A1

公开(公告)日：2012-03-01

申请号：US12872135

申请日：2010-08-31

Applicant: Jui-Jen WU ,  Shau-Wei LU ,  Robert LO ,  Kun-Hsi LI

Inventor： Jui-Jen WU ,  Shau-Wei LU ,  Robert LO ,  Kun-Hsi LI

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G11C7/1015 ,  G11C11/412 ,  G11C11/413

Abstract: A memory includes a memory cell, two word lines coupled to the memory cell, two bit lines coupled to the memory cell, and a write assist cell. The write assist cell is configured to transfer data of one bit line in a write operation to the other bit line in a read operation when one word line is used for the write operation, the other word line is used for the read operation, and the two word lines are asserted simultaneously.

Abstract translation: 存储器包括存储器单元，耦合到存储器单元的两个字线，耦合到存储器单元的两个位线以及写入辅助单元。 写入辅助单元被配置为当一个字线用于写入操作时，在读取操作中将写入操作中的一个位线的数据传送到另一个位线，另一个字线用于读取操作，并且 两个字线同时被断言。