公开(公告)号：US20190206986A1

公开(公告)日：2019-07-04

申请号：US15076553

申请日：2016-03-21

申请人： Jun Hu ,  Zhiyun Luo ,  Fei Wang

发明人： Jun Hu ,  Zhiyun Luo ,  Fei Wang

IPC分类号： H01L29/06 ,  H01L21/266 ,  H01L21/761

CPC分类号： H01L29/0623 ,  H01L21/266 ,  H01L21/761 ,  H01L29/7811 ,  H01L29/7823

摘要： This invention discloses a semiconductor power device formed on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The termination area comprises a plurality of duplicated units wherein each unit includes at least two trenches filled with a conductive trench material having a mesa area between adjacent trenches wherein the trenches and the mesa areas within each of the duplicated units are electrically shunt together. In the termination area each of the trenches in the duplicated units has a buried guard ring dopant region disposed below a bottom surface of the trenches.

公开(公告)号：US10038089B2

公开(公告)日：2018-07-31

申请号：US14957570

申请日：2015-12-02

申请人： Jun Hu ,  Zhiyun Luo ,  Fei Wang ,  Mengyu Pan

发明人： Jun Hu ,  Zhiyun Luo ,  Fei Wang ,  Mengyu Pan

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/32 ,  H01L29/10 ,  H01L29/40 ,  H01L21/3213

CPC分类号： H01L29/7813 ,  H01L21/32139 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/66734 ,  H01L29/7811

摘要： A semiconductor power device includes a plurality of power transistor cells each having a trenched gate disposed in a gate trench opened in a semiconductor substrate wherein a plurality of the trenched gates further include a shielded bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed at a top portion of the gate trench by an inter-electrode insulation layer. At least one of the shielded bottom electrode is connected a source metal and at least one of the top electrodes in the gate trench is connected to a source metal of the power device.

公开(公告)号：US11101346B2

公开(公告)日：2021-08-24

申请号：US15076553

申请日：2016-03-21

申请人： Jun Hu ,  Zhiyun Luo ,  Fei Wang

发明人： Jun Hu ,  Zhiyun Luo ,  Fei Wang

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/266 ,  H01L21/761

摘要： This invention discloses a semiconductor power device formed on a semiconductor substrate comprises an active cell area and a termination area disposed near edges of the semiconductor substrate. The termination area comprises a plurality of duplicated units wherein each unit includes at least two trenches filled with a conductive trench material having a mesa area between adjacent trenches wherein the trenches and the mesa areas within each of the duplicated units are electrically shunt together. In the termination area each of the trenches in the duplicated units has a buried guard ring dopant region disposed below a bottom surface of the trenches.

公开(公告)号：US20110254084A1

公开(公告)日：2011-10-20

申请号：US13039089

申请日：2011-03-02

申请人： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

发明人： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

IPC分类号： H01L29/78 ,  H01L21/76

CPC分类号： H01L29/7813 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66734

摘要： First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

摘要翻译： 第一多晶硅（poly-1）沉积在已经形成在衬底中的深沟槽中。 执行第一多晶硅抛光工艺以平坦化多晶硅-1的暴露表面，使得表面与相邻表面齐平。 然后，在深沟槽之间的衬底中形成浅沟槽，并且将第二多晶硅（poly-2）沉积到浅沟槽中。 执行第二多晶硅抛光工艺以平坦化多晶硅-2的暴露表面，使得表面与相邻表面齐平。 然后形成与poly-1和poly-2的金属接触。

公开(公告)号：US09577089B2

公开(公告)日：2017-02-21

申请号：US13039089

申请日：2011-03-02

申请人： Kyle Terrill ,  Deva Pattanayak ,  Zhiyun Luo

发明人： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

IPC分类号： H01L21/76 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/7813 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66734

摘要： First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

摘要翻译： 第一多晶硅（poly-1）沉积在已经形成在衬底中的深沟槽中。 执行第一多晶硅抛光工艺以平坦化多晶硅-1的暴露表面，使得表面与相邻表面齐平。 然后，在深沟槽之间的衬底中形成浅沟槽，并且将第二多晶硅（poly-2）沉积到浅沟槽中。 执行第二多晶硅抛光工艺以平坦化多晶硅-2的暴露表面，使得表面与相邻表面齐平。 然后形成与poly-1和poly-2的金属接触。