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    STRUCTURES AND METHODS OF FABRICATING DUAL GATE DEVICES
    1.
    发明申请
    STRUCTURES AND METHODS OF FABRICATING DUAL GATE DEVICES 有权
    双门装置的结构和方法

    公开(公告)号：US20110254084A1

    公开(公告)日：2011-10-20

    申请号：US13039089

    申请日：2011-03-02

    申请人： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

    发明人： Kyle Terrill ,  Yuming Bai ,  Deva Pattanayak ,  Zhiyun Luo

    IPC分类号： H01L29/78 ,  H01L21/76

    CPC分类号： H01L29/7813 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66734

    摘要： First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

    摘要翻译： 第一多晶硅（poly-1）沉积在已经形成在衬底中的深沟槽中。 执行第一多晶硅抛光工艺以平坦化多晶硅-1的暴露表面，使得表面与相邻表面齐平。 然后，在深沟槽之间的衬底中形成浅沟槽，并且将第二多晶硅（poly-2）沉积到浅沟槽中。 执行第二多晶硅抛光工艺以平坦化多晶硅-2的暴露表面，使得表面与相邻表面齐平。 然后形成与poly-1和poly-2的金属接触。

    Super trench MOSFET including buried source electrode and method of fabricating the same
    3.
    发明授权
    Super trench MOSFET including buried source electrode and method of fabricating the same 有权
    包括埋地源极的超级沟槽MOSFET及其制造方法

    公开(公告)号：US07183610B2

    公开(公告)日：2007-02-27

    申请号：US10836833

    申请日：2004-04-30

    申请人： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

    发明人： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

    摘要： In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

    摘要翻译： 在沟槽MOSFET中，沟槽的下部包含与外延层和半导体衬底绝缘但与源极区域电接触的掩埋源电极。 当MOSFET处于“关闭”状态时，掩埋源电极的偏置导致台面的“漂移”区域耗尽，增强了MOSFET阻止电流的能力。 因此，可以增加漂移区的掺杂浓度，从而降低MOSFET的导通电阻。 埋入式源极还降低了MOSFET的栅 - 漏电容，提高了MOSFET在高频下的工作能力。 衬底可以有利地包括由环形台面分隔开的多个环形沟槽和从源极金属区域分开的多个栅极金属腿中的中心区域向外延伸的栅极金属层。

    Method and circuits for reducing dead time and reverse recovery loss in buck regulators
    4.
    发明授权
    Method and circuits for reducing dead time and reverse recovery loss in buck regulators 失效
    降压稳压​​器中减少死区时间和反向恢复损耗的方法和电路

    公开(公告)号：US06737842B2

    公开(公告)日：2004-05-18

    申请号：US10268912

    申请日：2002-10-11

    申请人： Yuming Bai ,  Nick Sun ,  Alex Q. Huang

    发明人： Yuming Bai ,  Nick Sun ,  Alex Q. Huang

    IPC分类号： G05F1656

    CPC分类号： H02M3/1588 ,  H02M1/38 ,  Y02B70/1466

    摘要： A buck regulator having a voltage sensor for sensing a voltage reversal caused by freewheeling current from an output inductor in the regulator. Upon sensing a reversed voltage, the voltage sensor triggers a gate controller to turn on a switch in the regulator, and thereby terminate a dead time. The voltage sensor and gate controller are high speed circuits, and therefore can reduce the duration of the dead time. Reducing the dead time duration improves efficiency by reducing the duration of body diode conduction. The dead time can be reduced to less than a turn-on time of the body diode, thereby preventing charge buildup in the body diode, and, consequently, preventing reverse recovery loss in the body diode. The present invention improves electrical conversion efficiency, and allows for increased operating frequency in buck regulators.

    摘要翻译： 具有用于感测由调节器中的输出电感器的续流电流引起的电压反转的电压传感器的降压调节器。 在感测到反向电压时，电压传感器触发门控制器以打开调节器中的开关，从而终止死区时间。 电压传感器和门控制器是高速电路，因此可以减少死区时间。 减少死区时间可以通过减少体二极管导通的持续时间来提高效率。 死区时间可以减小到小于体二极管的导通时间，从而防止体二极管中的电荷累积，并且因此防止体二极管中的反向恢复损耗。 本发明提高了电转换效率，并且允许在降压调节器中提高工作频率。

    Structure and fabrication process of super junction MOSFET
    5.
    发明授权
    Structure and fabrication process of super junction MOSFET 失效
    超结MOSFET的结构和制造工艺

    公开(公告)号：US08604541B2

    公开(公告)日：2013-12-10

    申请号：US13441101

    申请日：2012-04-06

    申请人： Qin Huang ,  Yuming Bai ,  Yang Gao

    发明人： Qin Huang ,  Yuming Bai ,  Yang Gao

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7396

    摘要： This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.

    摘要翻译： 本发明公开了一种具体的超结MOSFET结构及其制造工艺。 这种结构包括：漏极，衬底，EPI，源极，侧壁隔离结构，栅极，栅极隔离层和源极。 在源下面的活动区域内有隔离层。 沿着该隔离层的侧壁，可以引入与主体相同的掺杂类型的缓冲层，并且还可以将源延伸以形成场板。 这种缓冲层和场板可以使EPI掺杂比常规器件高得多，这导致较低的Rdson，更好的性能，更短的栅极，从而减小栅极电荷Qg和栅极至漏极电荷Qgd。 制造这种结构的过程更简单，更具成本效益。

    STRUCTURE AND FABRICATION PROCESS OF SUPER JUNCTION MOSFET
    6.
    发明申请
    STRUCTURE AND FABRICATION PROCESS OF SUPER JUNCTION MOSFET 失效
    超级结MOSFET的结构与制造工艺

    公开(公告)号：US20120256254A1

    公开(公告)日：2012-10-11

    申请号：US13441101

    申请日：2012-04-06

    申请人： Qin HUANG ,  Yuming BAI ,  Yang GAO

    发明人： Qin HUANG ,  Yuming BAI ,  Yang GAO

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7802 ,  H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/66727 ,  H01L29/7396

    摘要： This invention discloses a specific superjunction MOSFET structure and its fabrication process. Such structure includes: a drain, a substrate, an EPI, a source, a side-wall isolation structure, a gate, a gate isolation layer and source. There is an isolation layer inside the active area underneath the source. Along the side-wall of this isolation layer, a buffer layer with same doping type as body can be introduced & source can be extended down too to form field plate. Such buffer layer & field plate can make the EPI doping much higher than convention device which results in lower Rdson, better performance, shorter gate so that to reduce both gate charge Qg and gate-to-drain charge Qgd. The process to make such structure is simpler and more cost effective.

    摘要翻译： 本发明公开了一种具体的超结MOSFET结构及其制造工艺。 这种结构包括：漏极，衬底，EPI，源极，侧壁隔离结构，栅极，栅极隔离层和源极。 在源下面的活动区域内有隔离层。 沿着该隔离层的侧壁，可以引入与主体相同的掺杂类型的缓冲层，并且还可以将源延伸以形成场板。 这种缓冲层和场板可以使EPI掺杂比常规器件高得多，这导致较低的Rdson，更好的性能，更短的栅极，从而减小栅极电荷Qg和栅极至漏极电荷Qgd。 制造这种结构的过程更简单，更具成本效益。

    Method of fabricating super trench MOSFET including buried source electrode
    7.
    发明申请
    Method of fabricating super trench MOSFET including buried source electrode 失效
    制造包括埋地源电极的超级沟槽MOSFET的方法

    公开(公告)号：US20080182376A1

    公开(公告)日：2008-07-31

    申请号：US12080031

    申请日：2008-03-31

    申请人： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

    发明人： Deva N. Pattanayak ,  Yuming Bai ,  Kyle Terrill ,  Christiana Yue ,  Robert Xu ,  Kam Hong Lui ,  Kuo-In Chen ,  Sharon Shi

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7811

    摘要： In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.

    摘要翻译： 在沟槽MOSFET中，沟槽的下部包含与外延层和半导体衬底绝缘但与源极区域电接触的掩埋源电极。 当MOSFET处于“关闭”状态时，掩埋源电极的偏置导致台面的“漂移”区域耗尽，增强了MOSFET阻止电流的能力。 因此，可以增加漂移区的掺杂浓度，从而降低MOSFET的导通电阻。 埋入式源极还降低了MOSFET的栅 - 漏电容，提高了MOSFET在高频下的工作能力。 衬底可以有利地包括由环形台面分隔开的多个环形沟槽和从源极金属区域分开的多个栅极金属腿中的中心区域向外延伸的栅极金属层。

    Structures for power transistor and methods of manufacture
    10.
    发明授权
    Structures for power transistor and methods of manufacture 有权
    功率晶体管和制造方法的结构

    公开(公告)号：US08823098B2

    公开(公告)日：2014-09-02

    申请号：US13414292

    申请日：2012-03-07

    申请人： Qin Huang ,  Yuming Bai

    发明人： Qin Huang ,  Yuming Bai

    IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/788 ,  H01L29/78 ,  H01L29/423 ,  H01L29/739 ,  H01L29/10 ,  H01L29/08 ,  H01L29/417

    CPC分类号： H01L29/7802 ,  H01L29/0834 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/7396

    摘要： The invention discloses a manufacture method and structure of a power transistor, comprising a lower electrode, a substrate, a drift region, two first conductive regions, two second conductive regions, two gate units, an isolation structure and an upper electrode. The two second conductive region are between the two first conductive regions and the drift region; the two gate units are on the two second conductive regions; the isolation structure covers the two gate units; the upper electrode covers the isolation structure and connects to the two first conductive regions and the two second conductive regions electrically. When the substrate is of the first conductive type, the structure can be used as MOSFET. When the substrate is of the second conductive type, the structure can be used as IGBT. This structure has a small gate electrode area, which leads to less Qg, Qgd and Rdson and improves device performance.

    摘要翻译： 本发明公开了一种功率晶体管的制造方法和结构，包括下电极，衬底，漂移区，两个第一导电区，两个第二导电区，两个栅极单元，隔离结构和上电极。 两个第二导电区域在两个第一导电区域和漂移区域之间; 两个栅极单元在两个第二导电区域上; 隔离结构覆盖两个门单元; 上电极覆盖隔离结构并且电连接到两个第一导电区域和两个第二导电区域。 当衬底是第一导电类型时，该结构可以用作MOSFET。 当基板是第二导电类型时，该结构可以用作IGBT。 该结构具有较小的栅电极面积，导致Qg，Qgd和Rdson较少，提高器件性能。