公开(公告)号：US07555699B2

公开(公告)日：2009-06-30

申请号：US11236610

申请日：2005-09-28

申请人： Masahiro Kuramoto ,  Masao Koyabu ,  Jun Tsuiki ,  Junichi Inagaki

发明人： Masahiro Kuramoto ,  Masao Koyabu ,  Jun Tsuiki ,  Junichi Inagaki

IPC分类号： G11C29/00

CPC分类号： G06F11/1016

摘要： A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.

摘要翻译： 一种用于存储控制电路中的地址错误检查的方法，该存储控制电路具有可操作以将数据存储在由地址指定的存储区域中的数据的存储单元，对分配给偶数位的地址的第一代码进行编码，分配给数据的第二代码 以奇数位写入存储单元，根据第一和第二代码产生一个校验码，并将校验码存储在存储单元中，与写入存储单元的数据相对应，并进行基于 从存储单元读取的数据，与读取的数据相对应的校验码和读取地址，从而检测多位地址错误。

公开(公告)号：US07475170B2

公开(公告)日：2009-01-06

申请号：US11187895

申请日：2005-07-25

申请人： Junichi Inagaki ,  Masao Koyabu ,  Jun Tsuiki ,  Masahiro Kuramoto

发明人： Junichi Inagaki ,  Masao Koyabu ,  Jun Tsuiki ,  Masahiro Kuramoto

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G06F13/4027 ,  G06F13/1673

摘要： The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.

摘要翻译： 本发明是一种数据传送装置，包括输入/​​输出接收缓冲器，输入/输出传输缓冲器，写数据缓冲器，读数据缓冲器，控制信息表，写数据存储处理部分，写数据 发送部分，读取数据缓冲存储处理部分，输入/输出发送缓冲存储处理部分和控制部分，其执行用于通过写入数据发送部分和读取数据缓冲存储处理部分来控制对存储器的访问的访问控制 基于控制信息表; 从而获得对存储器总线和输入/输出总线的两个协议最佳的配置，并且也可以实现无序执行。

公开(公告)号：US07602868B2

公开(公告)日：2009-10-13

申请号：US11341605

申请日：2006-01-30

申请人： Jun Tsuiki ,  Masao Koyabu ,  Masahiro Kuramoto ,  Junichi Inagaki

发明人： Jun Tsuiki ,  Masao Koyabu ,  Masahiro Kuramoto ,  Junichi Inagaki

IPC分类号： H04L7/00

CPC分类号： H04L7/00 ,  H04L7/0091

摘要： The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead. The asynchronous transmission device that receives at least one notification signal in accordance with a reception clock, the notification signal being transmitted in accordance with a transmission clock, includes a trigger signal transmission unit that outputs a trigger signal which is based on the symbol period of the notification signal, a notification signal transmission unit that outputs a notification signal which has its timing staggered by a predetermined time period with respect to the timing of the trigger signal output from the trigger signal transmission unit, a trigger signal synchronization unit that synchronizes the trigger signal, and outputs a sampling timing signal which indicates the sampling timing of the notification signal, and a notification signal retention unit that retains the notification signal in accordance with the sampling timing.

摘要翻译： 本发明提供了减少同步处理开销的异步传输装置和异步传输方法。 根据接收时钟接收至少一个通知信号的异步发送装置，根据传输时钟发送的通知信号包括：触发信号发送单元，其输出基于该信号的符号周期的触发信号 通知信号，通知信号发送单元，其相对于从触发信号发送单元输出的触发信号的定时输出其定时与预定时间段交错的通知信号;触发信号同步单元，其将触发信号 并输出指示通知信号的采样定时的采样定时信号，以及根据采样定时保持通知信号的通知信号保持单元。

公开(公告)号：US20070116165A1

公开(公告)日：2007-05-24

申请号：US11341605

申请日：2006-01-30

申请人： Jun Tsuiki ,  Masao Koyabu ,  Masahiro Kuramoto ,  Junichi Inagaki

发明人： Jun Tsuiki ,  Masao Koyabu ,  Masahiro Kuramoto ,  Junichi Inagaki

IPC分类号： H04L7/00

CPC分类号： H04L7/00 ,  H04L7/0091

摘要： The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead. The asynchronous transmission device that receives at least one notification signal in accordance with a reception clock, the notification signal being transmitted in accordance with a transmission clock, includes a trigger signal transmission unit that outputs a trigger signal which is based on the symbol period of the notification signal, a notification signal transmission unit that outputs a notification signal which has its timing staggered by a predetermined time period with respect to the timing of the trigger signal output from the trigger signal transmission unit, a trigger signal synchronization unit that synchronizes the trigger signal, and outputs a sampling timing signal which indicates the sampling timing of the notification signal, and a notification signal retention unit that retains the notification signal in accordance with the sampling timing.

摘要翻译： 本发明提供了减少同步处理开销的异步传输装置和异步传输方法。 根据接收时钟接收至少一个通知信号的异步发送装置，根据传输时钟发送的通知信号包括：触发信号发送单元，其输出基于该信号的符号周期的触发信号 通知信号，通知信号发送单元，其相对于从触发信号发送单元输出的触发信号的定时输出其定时与预定时间段交错的通知信号;触发信号同步单元，其将触发信号 并输出指示通知信号的采样定时的采样定时信号，以及根据采样定时保持通知信号的通知信号保持单元。

公开(公告)号：US20060236205A1

公开(公告)日：2006-10-19

申请号：US11236610

申请日：2005-09-28

申请人： Masahiro Kuramoto ,  Masao Koyabu ,  Jun Tsuiki ,  Junichi Inagaki

发明人： Masahiro Kuramoto ,  Masao Koyabu ,  Jun Tsuiki ,  Junichi Inagaki

IPC分类号： G11C29/00

CPC分类号： G06F11/1016

摘要： A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.

公开(公告)号：US20060212661A1

公开(公告)日：2006-09-21

申请号：US11187895

申请日：2005-07-25

申请人： Junichi Inagaki ,  Masao Koyabu ,  Jun Tsuiki ,  Masahiro Kuramoto

发明人： Junichi Inagaki ,  Masao Koyabu ,  Jun Tsuiki ,  Masahiro Kuramoto

IPC分类号： G06F13/28

CPC分类号： G06F13/4027 ,  G06F13/1673

摘要： The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.

摘要翻译： 本发明是一种数据传送装置，包括输入/​​输出接收缓冲器，输入/输出传输缓冲器，写数据缓冲器，读数据缓冲器，控制信息表，写数据存储处理部分，写数据 发送部分，读取数据缓冲存储处理部分，输入/输出发送缓冲存储处理部分和控制部分，其执行用于通过写入数据发送部分和读取数据缓冲存储处理部分来控制对存储器的访问的访问控制 基于控制信息表; 从而获得对存储器总线和输入/输出总线的两个协议最佳的配置，并且也可以实现无序执行。

公开(公告)号：US07756144B2

公开(公告)日：2010-07-13

申请号：US11472987

申请日：2006-06-23

申请人： Junichi Inagaki ,  Masao Koyabu

发明人： Junichi Inagaki ,  Masao Koyabu

IPC分类号： H04L12/56

CPC分类号： G06F15/17381

摘要： A parallel computer operates to reduce data held by a plurality of nodes. Each node constituting a parallel computer transfers the data divided into n to other nodes, and each node summarizes the respective 1/n data and operates, then a plurality of nodes transfer the respective operation result to a summarizing node. Since all the nodes execute operation for divided data respectively, reduction processing time can be decreased. And more nodes (network adapters) can participate in data transfer through the first and second data transfers, high-speed transfer processing can therefore be implemented, and transfer time can be decreased.

摘要翻译： 并行计算机操作以减少由多个节点保持的数据。 构成并行计算机的每个节点将分配为n的数据传送到其他节点，并且每个节点汇总相应的1 / n数据并进行操作，则多个节点将相应的运算结果传送到汇总节点。 由于所有节点分别执行分割数据的操作，所以可以减少缩短处理时间。 并且通过第一和第二数据传输，更多节点（网络适配器）可以参与数据传输，因此可以实现高速传输处理，并且可以减少传输时间。

公开(公告)号：US20070220164A1

公开(公告)日：2007-09-20

申请号：US11472987

申请日：2006-06-23

申请人： Junichi Inagaki ,  Masao Koyabu

发明人： Junichi Inagaki ,  Masao Koyabu

IPC分类号： G06F15/16

CPC分类号： G06F15/17381

摘要： A parallel computer operates to reduce data held by a plurality of nodes. Each node constituting a parallel computer transfers the data divided into n to other nodes, and each node summarizes the respective 1/n data and operates, then a plurality of nodes transfer the respective operation result to a summarizing node. Since all the nodes execute operation for divided data respectively, reduction processing time can be decreased. And more nodes (network adapters) can participate in data transfer through the first and second data transfers, high-speed transfer processing can therefore be implemented, and transfer time can be decreased.

摘要翻译： 并行计算机操作以减少由多个节点保持的数据。 构成并行计算机的每个节点将分配为n的数据传送到其他节点，并且每个节点汇总相应的1 / n数据并进行操作，则多个节点将相应的运算结果传送到汇总节点。 由于所有节点分别执行分割数据的操作，所以可以减少缩短处理时间。 并且通过第一和第二数据传输，更多节点（网络适配器）可以参与数据传输，因此可以实现高速传输处理，并且可以减少传输时间。

公开(公告)号：US20070217450A1

公开(公告)日：2007-09-20

申请号：US11472985

申请日：2006-06-23

申请人： Junichi Inagaki ,  Masao Koyabu

发明人： Junichi Inagaki ,  Masao Koyabu

IPC分类号： H04J3/24

CPC分类号： G06F15/17375

摘要： A network system broadcast data from one node to a plurality of other nodes, which can decrease the time required for broadcast. A transfer source node divides the transfer data to be broadcasted, and transfers each divided data separately from the network adapters of the transfer source node to the network adapters of the other nodes, and the other nodes transfer the received data to the network adapters of the other nodes other than the transfer source node. Since more nodes (network adapters) can participate in data transfer in the second data transfer, high-speed transfer processing can be implemented, and the transfer processing time for broadcast can be decreased.

摘要翻译： 网络系统从一个节点向多个其他节点广播数据，这可以减少广播所需的时间。 传输源节点划分要广播的传输数据，并将每个划分的数据与传输源节点的网络适配器分开传送到其他节点的网络适配器，而其他节点将接收到的数据传输到网络适配器 传输源节点以外的其他节点。 由于更多的节点（网络适配器）可以参与第二数据传输中的数据传输，所以可以实现高速传输处理，并且可以减少广播的传送处理时间。

公开(公告)号：US20070226288A1

公开(公告)日：2007-09-27

申请号：US11475048

申请日：2006-06-27

申请人： Junichi Inagaki ,  Masao Koyabu ,  Hiroaki Ishihata

发明人： Junichi Inagaki ,  Masao Koyabu ,  Hiroaki Ishihata

IPC分类号： G06F7/38

CPC分类号： G06F7/485 ,  G06F7/49942 ,  G06F7/509

摘要： A computer system execute summation processing even if the computing sequence is not adhered to in a system for computing a sum of floating point data of a plurality of nodes. Each node sends floating point data to a reduction mechanism, and the reduction mechanism computes the sums only for a group of which exponent sections have a highest value and a group of which exponent sections have a second highest value, and adds the sum of the group of which the exponent sections have a highest value and the sum of the group of which the exponent sections have a second highest value. By this, the consistency of the computation result can be guaranteed even if the sum is computed regardless the computing sequence of the values.

摘要翻译： 即使在用于计算多个节点的浮点数据的和的系统中不遵守计算顺序，计算机系统执行求和处理。 每个节点向减少机制发送浮点数据，并且减少机制仅针对指数部分具有最高值的组和一组指数部分具有第二高值来计算和，并且将该组的总和相加 其指数部分具有最高值，并且指数部分具有第二高值的组的总和。 由此，即使计算和不考虑值的计算顺序，也可以保证计算结果的一致性。