公开(公告)号：US07475170B2

公开(公告)日：2009-01-06

申请号：US11187895

申请日：2005-07-25

申请人： Junichi Inagaki ,  Masao Koyabu ,  Jun Tsuiki ,  Masahiro Kuramoto

发明人： Junichi Inagaki ,  Masao Koyabu ,  Jun Tsuiki ,  Masahiro Kuramoto

IPC分类号： G06F3/00 ,  G06F12/00

CPC分类号： G06F13/4027 ,  G06F13/1673

摘要： The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.

摘要翻译： 本发明是一种数据传送装置，包括输入/​​输出接收缓冲器，输入/输出传输缓冲器，写数据缓冲器，读数据缓冲器，控制信息表，写数据存储处理部分，写数据 发送部分，读取数据缓冲存储处理部分，输入/输出发送缓冲存储处理部分和控制部分，其执行用于通过写入数据发送部分和读取数据缓冲存储处理部分来控制对存储器的访问的访问控制 基于控制信息表; 从而获得对存储器总线和输入/输出总线的两个协议最佳的配置，并且也可以实现无序执行。

公开(公告)号：US07555699B2

公开(公告)日：2009-06-30

申请号：US11236610

申请日：2005-09-28

申请人： Masahiro Kuramoto ,  Masao Koyabu ,  Jun Tsuiki ,  Junichi Inagaki

发明人： Masahiro Kuramoto ,  Masao Koyabu ,  Jun Tsuiki ,  Junichi Inagaki

IPC分类号： G11C29/00

CPC分类号： G06F11/1016

摘要： A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.

摘要翻译： 一种用于存储控制电路中的地址错误检查的方法，该存储控制电路具有可操作以将数据存储在由地址指定的存储区域中的数据的存储单元，对分配给偶数位的地址的第一代码进行编码，分配给数据的第二代码 以奇数位写入存储单元，根据第一和第二代码产生一个校验码，并将校验码存储在存储单元中，与写入存储单元的数据相对应，并进行基于 从存储单元读取的数据，与读取的数据相对应的校验码和读取地址，从而检测多位地址错误。

公开(公告)号：US20060236205A1

公开(公告)日：2006-10-19

申请号：US11236610

申请日：2005-09-28

申请人： Masahiro Kuramoto ,  Masao Koyabu ,  Jun Tsuiki ,  Junichi Inagaki

发明人： Masahiro Kuramoto ,  Masao Koyabu ,  Jun Tsuiki ,  Junichi Inagaki

IPC分类号： G11C29/00

CPC分类号： G06F11/1016

摘要： A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.

公开(公告)号：US20060212661A1

公开(公告)日：2006-09-21

申请号：US11187895

申请日：2005-07-25

申请人： Junichi Inagaki ,  Masao Koyabu ,  Jun Tsuiki ,  Masahiro Kuramoto

发明人： Junichi Inagaki ,  Masao Koyabu ,  Jun Tsuiki ,  Masahiro Kuramoto

IPC分类号： G06F13/28

CPC分类号： G06F13/4027 ,  G06F13/1673

摘要： The present invention is a data transfer device, which comprises an input/output reception buffer, an input/output transmission buffer, a write data buffer, a read data buffer, a control information table, a write data storing process section, a write data transmission section, a read data buffer storing process section, an input/output transmission buffer storing process section and a control section that executes an access control for controlling the access to the memory by the write data transmission section and the read data buffer storing process section based on a control information table; thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.

摘要翻译： 本发明是一种数据传送装置，包括输入/​​输出接收缓冲器，输入/输出传输缓冲器，写数据缓冲器，读数据缓冲器，控制信息表，写数据存储处理部分，写数据 发送部分，读取数据缓冲存储处理部分，输入/输出发送缓冲存储处理部分和控制部分，其执行用于通过写入数据发送部分和读取数据缓冲存储处理部分来控制对存储器的访问的访问控制 基于控制信息表; 从而获得对存储器总线和输入/输出总线的两个协议最佳的配置，并且也可以实现无序执行。

公开(公告)号：US07602868B2

公开(公告)日：2009-10-13

申请号：US11341605

申请日：2006-01-30

申请人： Jun Tsuiki ,  Masao Koyabu ,  Masahiro Kuramoto ,  Junichi Inagaki

发明人： Jun Tsuiki ,  Masao Koyabu ,  Masahiro Kuramoto ,  Junichi Inagaki

IPC分类号： H04L7/00

CPC分类号： H04L7/00 ,  H04L7/0091

摘要： The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead. The asynchronous transmission device that receives at least one notification signal in accordance with a reception clock, the notification signal being transmitted in accordance with a transmission clock, includes a trigger signal transmission unit that outputs a trigger signal which is based on the symbol period of the notification signal, a notification signal transmission unit that outputs a notification signal which has its timing staggered by a predetermined time period with respect to the timing of the trigger signal output from the trigger signal transmission unit, a trigger signal synchronization unit that synchronizes the trigger signal, and outputs a sampling timing signal which indicates the sampling timing of the notification signal, and a notification signal retention unit that retains the notification signal in accordance with the sampling timing.

摘要翻译： 本发明提供了减少同步处理开销的异步传输装置和异步传输方法。 根据接收时钟接收至少一个通知信号的异步发送装置，根据传输时钟发送的通知信号包括：触发信号发送单元，其输出基于该信号的符号周期的触发信号 通知信号，通知信号发送单元，其相对于从触发信号发送单元输出的触发信号的定时输出其定时与预定时间段交错的通知信号;触发信号同步单元，其将触发信号 并输出指示通知信号的采样定时的采样定时信号，以及根据采样定时保持通知信号的通知信号保持单元。

公开(公告)号：US20070116165A1

公开(公告)日：2007-05-24

申请号：US11341605

申请日：2006-01-30

申请人： Jun Tsuiki ,  Masao Koyabu ,  Masahiro Kuramoto ,  Junichi Inagaki

发明人： Jun Tsuiki ,  Masao Koyabu ,  Masahiro Kuramoto ,  Junichi Inagaki

IPC分类号： H04L7/00

CPC分类号： H04L7/00 ,  H04L7/0091

摘要： The present invention provides an asynchronous transmission device and asynchronous transmission method which reduce the synchronization processing overhead. The asynchronous transmission device that receives at least one notification signal in accordance with a reception clock, the notification signal being transmitted in accordance with a transmission clock, includes a trigger signal transmission unit that outputs a trigger signal which is based on the symbol period of the notification signal, a notification signal transmission unit that outputs a notification signal which has its timing staggered by a predetermined time period with respect to the timing of the trigger signal output from the trigger signal transmission unit, a trigger signal synchronization unit that synchronizes the trigger signal, and outputs a sampling timing signal which indicates the sampling timing of the notification signal, and a notification signal retention unit that retains the notification signal in accordance with the sampling timing.

摘要翻译： 本发明提供了减少同步处理开销的异步传输装置和异步传输方法。 根据接收时钟接收至少一个通知信号的异步发送装置，根据传输时钟发送的通知信号包括：触发信号发送单元，其输出基于该信号的符号周期的触发信号 通知信号，通知信号发送单元，其相对于从触发信号发送单元输出的触发信号的定时输出其定时与预定时间段交错的通知信号;触发信号同步单元，其将触发信号 并输出指示通知信号的采样定时的采样定时信号，以及根据采样定时保持通知信号的通知信号保持单元。

公开(公告)号：US06570424B2

公开(公告)日：2003-05-27

申请号：US10102767

申请日：2002-03-22

申请人： Jun Tsuiki ,  Toshiyuki Shimizu

发明人： Jun Tsuiki ,  Toshiyuki Shimizu

IPC分类号： H03H1116

CPC分类号： H04L7/04 ,  H03L7/00 ,  H04L7/0337

摘要： A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.

公开(公告)号：US08775679B2

公开(公告)日：2014-07-08

申请号：US12588915

申请日：2009-11-02

申请人： Hiroyuki Oka ,  Jun Tsuiki

发明人： Hiroyuki Oka ,  Jun Tsuiki

IPC分类号： G06F15/16

CPC分类号： H04L12/462 ,  G06F9/52

摘要： Provided is a device for issuing a synchronization message in a large-scaled computing system including an interconnect and a plurality of computing devices that is connected to the interconnect. The interconnect includes a plurality of switches that is connected to each other. The device sends a synchronization message for synchronizing computing processes on the computing devices to all the computing devices at same timing via the switches that are directly connected to any of the computing devices by using a protocol for a general-purpose interconnect.

摘要翻译： 提供了一种用于在大规模计算系统中发布同步消息的设备，包括互连和连接到互连的多个计算设备。 互连包括彼此连接的多个开关。 设备通过使用用于通用互连的协议，经由直接连接到任何计算设备的交换机，在相同的定时向计算设备发送用于将计算设备上的计算过程同步到所有计算设备的同步消息。

公开(公告)号：US20100111115A1

公开(公告)日：2010-05-06

申请号：US12461019

申请日：2009-07-29

申请人： Jun Tsuiki ,  Hiroyuki Oka

发明人： Jun Tsuiki ,  Hiroyuki Oka

IPC分类号： H04J3/06

CPC分类号： H04L67/104 ,  H04L67/1095 ,  H04W4/02

摘要： A node-to-node synchronizing apparatus includes an information generating unit. Before receiving a synchronization request for synchronization, the information generating unit receives, from each process in each computing node, a mask generation request requesting to generate process location information (mask) indicating the location of processes that participate in synchronization. The information generating unit then automatically generates the process location information based on the mask generation request.

摘要翻译： 节点到节点同步装置包括信息生成单元。 在接收到用于同步的同步请求之前，信息生成单元从每个计算节点中的每个进程接收请求生成指示参与同步的进程的位置的处理位置信息（掩码）的掩码生成请求。 然后，信息生成单元基于掩码生成请求自动生成处理位置信息。

公开(公告)号：US06586983B2

公开(公告)日：2003-07-01

申请号：US10102768

申请日：2002-03-22

申请人： Jun Tsuiki ,  Toshiyuki Shimizu

发明人： Jun Tsuiki ,  Toshiyuki Shimizu

IPC分类号： H03H1116

CPC分类号： H04L7/04 ,  H03L7/00 ,  H04L7/0337

摘要： A signal phase adjustment circuit to set an optimum phase by adjusting the difference in delay times between signal lines even when the distribution of the amount of phase modification that can be received normally is divided into a plurality of continuous regions. The amount of phase modification of the transmitted signal is allowed to fluctuate during one cycle of the operational frequency of the circuit. Determination of whether or not the reception signal during this interval can be received is continued, and the distribution of amount of phase modification that can be normally received is detected. The detected amount of phase modification defines continuous regions, and an optimum phase region is specified by selecting a region having a width of a specified value or more or the region having the greatest width. The optimum amount of sampling phase modification is determined from the upper and lower limit values of this region.