公开(公告)号：US20060113571A1

公开(公告)日：2006-06-01

申请号：US11136810

申请日：2005-05-24

申请人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Huang

发明人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Huang

IPC分类号： H01L29/768

CPC分类号： H01L21/761 ,  H01L21/76232 ,  H01L27/088 ,  H01L27/0921

摘要： A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.

摘要翻译： 半导体结构包括设置在半导体衬底上的隔离环，围绕第一和第二电路区域。 掩埋隔离层在半导体衬底中连续延伸穿过第一电路区域和第二电路区域。 掩埋隔离层与隔离环接合，从而将第一和第二电路区域与半导体衬底的背面偏置隔离。 离子增强隔离层将第一电路区域中的第一阱和第二电路区域中的第二阱与隔离环和掩埋隔离层分离，从而防止电路区域的阱和掩埋隔离层之间的穿通 。

公开(公告)号：US07196392B2

公开(公告)日：2007-03-27

申请号：US11136810

申请日：2005-05-24

申请人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Po Huang

发明人： Jun-Xiu Liu ,  Chi-Hsuen Chang ,  Tzu-Chiang Sung ,  Chung-I Chen ,  Chih Po Huang

IPC分类号： H01L29/00

CPC分类号： H01L21/761 ,  H01L21/76232 ,  H01L27/088 ,  H01L27/0921

摘要： A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor substrate. The buried isolation layer interfaces with the isolation ring, thereby isolating the first and second circuit areas from a backside bias of the semiconductor substrate. An ion enhanced isolation layer separates the first well in the first circuit area and the second well in the second circuit areas from the isolation ring and the buried isolation layer, thereby preventing punch-through between the wells of the circuit areas and the buried isolation layer.

摘要翻译： 半导体结构包括设置在半导体衬底上的隔离环，围绕第一和第二电路区域。 掩埋隔离层在半导体衬底中连续延伸穿过第一电路区域和第二电路区域。 掩埋隔离层与隔离环接合，从而将第一和第二电路区域与半导体衬底的背面偏置隔离。 离子增强隔离层将第一电路区域中的第一阱和第二电路区域中的第二阱与隔离环和掩埋隔离层分离，从而防止电路区域的阱和掩埋隔离层之间的穿通 。

公开(公告)号：US06734511B2

公开(公告)日：2004-05-11

申请号：US10001113

申请日：2001-11-02

申请人： Jun-Xiu Liu ,  Ming-Shuo Yen ,  Chiu-Bian Kuo ,  Chun-Hsiung Peng

发明人： Jun-Xiu Liu ,  Ming-Shuo Yen ,  Chiu-Bian Kuo ,  Chun-Hsiung Peng

IPC分类号： H01L2706

CPC分类号： H01L21/76877 ,  H01L21/76892

摘要： A method and system for implementing a variable function circuit within a single semiconductor chip. The semiconductor chip can be configured as a single circuit that provides varying functions according to extrinsic conditions. The single circuit can be permitted to be switched between a particular function and a different particular function, thereby promoting a decreased complexity in circuit design and a decrease in physical dimensions necessary to manufacture the semiconductor chip. Additionally, at least one portion of the semiconductor chip may be designated to the particular function and at least one other portion of the semiconductor chip to the different particular function. The semiconductor chip may thus act as a function switch.

摘要翻译： 一种用于在单个半导体芯片内实现可变功能电路的方法和系统。 半导体芯片可以被配置为根据外在条件提供变化的功能的单个电路。 可以允许单个电路在特定功能和不同的特定功能之间切换，从而促进电路设计的复杂性降低以及制造半导体芯片所需的物理尺寸的减小。 此外，可以将半导体芯片的至少一部分指定为特定功能，并将半导体芯片的至少一个其他部分指定为不同的特定功能。 因此，半导体芯片可以用作功能开关。