公开(公告)号：US06690027B1

公开(公告)日：2004-02-10

申请号：US10048719

申请日：2002-06-13

申请人： Daniel Bensahel ,  Yves Campidelli ,  Caroline Hernandez

发明人： Daniel Bensahel ,  Yves Campidelli ,  Caroline Hernandez

IPC分类号： H01L2706

CPC分类号： H01L33/34 ,  B82Y10/00 ,  B82Y20/00 ,  H01L21/30604 ,  H01L29/127 ,  H01L29/151 ,  H01S5/3227 ,  H01S5/3412

摘要： A method for forming on a Ge or Si monocrystalline substrate successive Si/Ge, Si/SiGe, or Si/SiGe/Ge layers for a Ge substrate and inversely for a Si substrate is described. Electrochemical treatment of the stack of layers to make the layers porous and form therein residual crystallites is also described. The invention may be used to provide devices having layers of planes of quantum drops.

摘要翻译： 描述了在Ge或Si单晶衬底上形成用于Ge衬底的连续Si / Ge，Si / SiGe或Si / SiGe / Ge层并且反向用于Si衬底的方法。 还描述了层叠层的电化学处理以使层多孔并在其中形成残余微晶。 本发明可以用于提供具有量子滴的平面层的器件。

公开(公告)号：US06455880B1

公开(公告)日：2002-09-24

申请号：US09434475

申请日：1999-11-05

申请人： Naoko Ono ,  Yuji Iseki ,  Keiichi Yamaguchi ,  Junko Onomura ,  Eiji Takagi

发明人： Naoko Ono ,  Yuji Iseki ,  Keiichi Yamaguchi ,  Junko Onomura ,  Eiji Takagi

IPC分类号： H01L2706

CPC分类号： H01P3/088 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L29/8126 ,  H01L2223/6627 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/4911 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/1903 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01P3/003 ,  H01L2924/00014 ,  H01L2924/00

摘要： A high frequency semiconductor device has a semiconductor substrate such as the semi-insulating GaAs; a first metal layer disposed above the semiconductor substrate; a first dielectric thin film disposed on the first metal layer; and a second metal layer having a second metal strip disposed on the first dielectric thin film. Here, the first metal layer has a first metal strip, first and second ground metal plates sandwiching the first metal strip. And the first dielectric thin film is not disposed uniformly on the surface of the first ground metal plate so that the dielectric structure on the first metal strip differs from the dielectric structure under the second metal strip. The CPW is constituted by the first metal strip, the first and second ground metal plates, and the TFMSL is constituted by the second metal strip and the first ground metal plate. By employing the structure such that there is no dielectric thin film on the CPW portion, or that the thickness of the dielectric thin film on the CPW portion is configured to be less than the thickness of the dielectric thin film associated with the TFMSL portion, the effective dielectric constant ∈eff of the CPW portion is made lower than that of the conventional CPW, which employs a uniform and homogenous dielectric structure so that the CPW portion has the same thickness of the TFMSL portion. As the result, the adjustable range of the characteristic impedance Z0 of the high frequency transmission line, merged in the high frequency semiconductor integrated circuit, increases. Then the high-performance integrated circuits such as MMICs having the low transmission loss, the low crosstalk can be achieved.

摘要翻译： 高频半导体器件具有诸如半绝缘GaAs的半导体衬底; 设置在所述半导体衬底上方的第一金属层; 设置在所述第一金属层上的第一电介质薄膜; 以及具有设置在第一介电薄膜上的第二金属条的第二金属层。 这里，第一金属层具有第一金属带，夹着第一金属带的第一和第二接地金属板。 并且第一电介质薄膜不均匀地设置在第一金属板的表面上，使得第一金属带上的电介质结构与第二金属带下的电介质结构不同。 CPW由第一金属带，第一和第二接地金属板构成，并且TFMSL由第二金属带和第一接地金属板构成。 通过采用在CPW部分上不存在电介质薄膜的结构，或者CPW部分上的电介质薄膜的厚度小于与TFMSL部分相关联的电介质薄膜的厚度， 使得CPW部分的有效介电常数εeff比常规CPW的有效介电常数εeff低，其采用均匀且均匀的电介质结构，使得CPW部分具有相同厚度的TFMSL部分。 结果，在高频半导体集成电路中合并的高频传输线的特性阻抗Z0的可调范围增加。 然后，可以实现具有低传输损耗，低串扰的高性能集成电路，例如MMIC。

公开(公告)号：US06483181B2

公开(公告)日：2002-11-19

申请号：US09837255

申请日：2001-04-19

申请人： Cecil Chang ,  Jansen Chiu

发明人： Cecil Chang ,  Jansen Chiu

IPC分类号： H01L2706

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip package with a LOC lead frame is disclosed. Such a LOC lead frame has a plurality of leads, with each lead being divided into an inner portion and an outer connecting portion. A first tape adhering under the inner portions of the leads fastens the first chip and the first bonding wires electrically connect the first chip with the inner portions. A second tape adhering upon the inner portions of the leads fastens the second chip and the second bonding wires electrically connect the second chip with the inner portions. The second tape has a thickness so as to avoid the first bonding wires touching the second chip. The multi-chip package enables to package at least two chips by a LOC lead frame without turnover action during wire-bonding.

摘要翻译： 公开了具有LOC引线框架的多芯片封装。 这种LOC引线框架具有多个引线，每个引线被分成内部部分和外部连接部分。 附着在引线的内部下方的第一带紧固第一芯片，并且第一接合线将第一芯片与内部部分电连接。 附着在引线的内部的第二带紧固第二芯片，第二接合线将第二芯片与内部部分电连接。 第二带具有厚度以避免第一接合线接触第二芯片。 多芯片封装使得能够在引线接合期间通过LOC引线框架封装至少两个芯片，而不会产生周转动作。

公开(公告)号：US06833606B2

公开(公告)日：2004-12-21

申请号：US10289684

申请日：2002-11-07

申请人： Hiroshi Nakamura ,  Ting Cheong Ang ,  Kian Siong Ang ,  Subrata Halder ,  Geok Ing Ng

发明人： Hiroshi Nakamura ,  Ting Cheong Ang ,  Kian Siong Ang ,  Subrata Halder ,  Geok Ing Ng

IPC分类号： H01L2706

CPC分类号： H01L27/0605 ,  H01L21/8252

摘要： In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

摘要翻译： 在本发明中，形成半导体器件，其包括位于异质结构的上表面上的MIM电容器，从其定义附近HBT的发射极，基极和集电极部分。 以这种方式，电容器和HBT分别具有基本上共同的结构，HBT的基极和发射极电极分别由与上部和下部电容器板相同的金属层制成。 此外，由于在定义HBT结构之前形成电容器的绝缘体区域，所以使用的电介质材料可以通过等离子体增强工艺沉积，而不会损坏HBT结构。

公开(公告)号：US06734511B2

公开(公告)日：2004-05-11

申请号：US10001113

申请日：2001-11-02

申请人： Jun-Xiu Liu ,  Ming-Shuo Yen ,  Chiu-Bian Kuo ,  Chun-Hsiung Peng

发明人： Jun-Xiu Liu ,  Ming-Shuo Yen ,  Chiu-Bian Kuo ,  Chun-Hsiung Peng

IPC分类号： H01L2706

CPC分类号： H01L21/76877 ,  H01L21/76892

摘要： A method and system for implementing a variable function circuit within a single semiconductor chip. The semiconductor chip can be configured as a single circuit that provides varying functions according to extrinsic conditions. The single circuit can be permitted to be switched between a particular function and a different particular function, thereby promoting a decreased complexity in circuit design and a decrease in physical dimensions necessary to manufacture the semiconductor chip. Additionally, at least one portion of the semiconductor chip may be designated to the particular function and at least one other portion of the semiconductor chip to the different particular function. The semiconductor chip may thus act as a function switch.

摘要翻译： 一种用于在单个半导体芯片内实现可变功能电路的方法和系统。 半导体芯片可以被配置为根据外在条件提供变化的功能的单个电路。 可以允许单个电路在特定功能和不同的特定功能之间切换，从而促进电路设计的复杂性降低以及制造半导体芯片所需的物理尺寸的减小。 此外，可以将半导体芯片的至少一部分指定为特定功能，并将半导体芯片的至少一个其他部分指定为不同的特定功能。 因此，半导体芯片可以用作功能开关。

公开(公告)号：US06376913B1

公开(公告)日：2002-04-23

申请号：US09374895

申请日：1999-08-13

申请人： Martin Buck

发明人： Martin Buck

IPC分类号： H01L2706

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/647 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2924/00

摘要： On the leads of an integrated semiconductor chip which establish a connection to external terminals of a supply voltage, highly clocked current pulses may result in the excitation of potential fluctuations through to resonance oscillations at an internal terminal of the respective lead. In order to attenuate these potential fluctuations, a resistance is prescribed for one or more leads, which resistance is large enough to attenuate the potential fluctuations but is small enough to cause only a predetermined maximum permissible voltage drop on the respective lead. The respective resistance can be obtained by using a material having a corresponding resistivity or by reducing the conductor cross section with a notch along the lead.

摘要翻译： 在建立与电源电压的外部端子的连接的集成半导体芯片的引线上，高时钟电流脉冲可能导致电位波动的激发通过相应引线的内部端子处的谐振振荡。 为了衰减这些电位波动，对一个或多个引线规定了电阻，该电阻足够大以使电位波动衰减，但是足够小以致仅导致相应引线上的预定的最大允许电压降。 可以通过使用具有相应电阻率的材料或通过沿着引线减少具有凹口的导体横截面来获得相应的电阻。

公开(公告)号：US06314387B1

公开(公告)日：2001-11-06

申请号：US09171531

申请日：1998-11-30

申请人： Hiroshi Kubo ,  Keishi Murakami

发明人： Hiroshi Kubo ,  Keishi Murakami

IPC分类号： H01L2706

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H04L1/0054 ,  H04L1/006

摘要： The prior art method of estimating a sequence by making use of a Viterbi algorithm is modified as follows: (1) A path at a certain past instant is modified to derive a modified path. (2) The path metric value of the modified path is calculated. (3) The path metric of a normal path and the path metric of the modified path are compared. If the path metric of the modified path is smaller, the path is modified. (4) A surviving path is selected from plural paths passing through the modified path.

摘要翻译： 通过使用维特比算法估计序列的现有技术方法如下修改：（1）修改某一过去时刻的路径以导出修改的路径。 （2）计算修改路径的路径度量值。 （3）比较正常路径的路径度量和修改路径的路径度量。 如果修改路径的路径度量较小，则修改路径。 （4）从通过修改路径的多个路径中选择存活路径。