公开(公告)号：US06734511B2

公开(公告)日：2004-05-11

申请号：US10001113

申请日：2001-11-02

申请人： Jun-Xiu Liu ,  Ming-Shuo Yen ,  Chiu-Bian Kuo ,  Chun-Hsiung Peng

发明人： Jun-Xiu Liu ,  Ming-Shuo Yen ,  Chiu-Bian Kuo ,  Chun-Hsiung Peng

IPC分类号： H01L2706

CPC分类号： H01L21/76877 ,  H01L21/76892

摘要： A method and system for implementing a variable function circuit within a single semiconductor chip. The semiconductor chip can be configured as a single circuit that provides varying functions according to extrinsic conditions. The single circuit can be permitted to be switched between a particular function and a different particular function, thereby promoting a decreased complexity in circuit design and a decrease in physical dimensions necessary to manufacture the semiconductor chip. Additionally, at least one portion of the semiconductor chip may be designated to the particular function and at least one other portion of the semiconductor chip to the different particular function. The semiconductor chip may thus act as a function switch.

摘要翻译： 一种用于在单个半导体芯片内实现可变功能电路的方法和系统。 半导体芯片可以被配置为根据外在条件提供变化的功能的单个电路。 可以允许单个电路在特定功能和不同的特定功能之间切换，从而促进电路设计的复杂性降低以及制造半导体芯片所需的物理尺寸的减小。 此外，可以将半导体芯片的至少一部分指定为特定功能，并将半导体芯片的至少一个其他部分指定为不同的特定功能。 因此，半导体芯片可以用作功能开关。

公开(公告)号：US07709908B2

公开(公告)日：2010-05-04

申请号：US11836785

申请日：2007-08-10

申请人： Chao-Yuan Su ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Chih-Jen Huang ,  Te-Yuan Wu ,  Chun-Hsiung Peng

发明人： Chao-Yuan Su ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Chih-Jen Huang ,  Te-Yuan Wu ,  Chun-Hsiung Peng

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/42368

摘要： A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first field plate rings. The first conductive layer is electrically connected to the drain and at least one of the first field plate rings.

摘要翻译： 高压晶体管器件具有衬底，隔离结构，源极，栅极，漏极，多个掺杂区域，多个离子阱以及设置在衬底上的第一介电层。 高压晶体管器件还具有第一导电层和多个第一场板环。 第一导电层电连接到漏极和至少一个第一场板环。

公开(公告)号：US20090111252A1

公开(公告)日：2009-04-30

申请号：US11928133

申请日：2007-10-30

申请人： Chih-Jen Huang ,  Ching-Ming Lee ,  Wei-Lun Hsu ,  Chao-Yuan Su ,  Chun-Hsiung Peng

发明人： Chih-Jen Huang ,  Ching-Ming Lee ,  Wei-Lun Hsu ,  Chao-Yuan Su ,  Chun-Hsiung Peng

IPC分类号： H01L21/265

CPC分类号： H01L29/0847 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of fabricating a deep well region of a high voltage device is provided. The method includes designating a deep well region that includes a designated highly doped region and a designed scarcely doped region in a substrate. A mask layer, which covers a periphery of the designated deep well region, is formed over the substrate, wherein the mask layer includes a plurality of shielding parts to cover a portion of the designated scarcely doped region. Using the mask layer as an implantation mask, an ion implantation process is performed to implant dopants into the substrate exposed by the mask and to form a plurality of undoped regions in the designated scarcely doped region covered by the shielding parts. The dopants in the designated scarcely doped region are then induced to diffuse to the undoped regions.

摘要翻译： 提供一种制造高压器件的深阱区域的方法。 该方法包括指定深阱区域，其包括指定的高掺杂区域和在衬底中设计的几乎不掺杂的区域。 覆盖指定的深阱区域的周边的掩模层形成在衬底上，其中掩模层包括多个屏蔽部分以覆盖指定的几乎不掺杂区域的一部分。 使用掩模层作为注入掩模，执行离子注入工艺以将掺杂剂注入到由掩模暴露的衬底中，并在由屏蔽部分覆盖的指定的几乎不掺杂的区域中形成多个未掺杂的区域。 然后诱导指定的稀少掺杂区域中的掺杂剂扩散到未掺杂的区域。

公开(公告)号：US20090039424A1

公开(公告)日：2009-02-12

申请号：US11836785

申请日：2007-08-10

申请人： Chao-Yuan Su ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Chih-Jen Huang ,  Te-Yuan Wu ,  Chun-Hsiung Peng

发明人： Chao-Yuan Su ,  Wei-Lun Hsu ,  Ching-Ming Lee ,  Chih-Jen Huang ,  Te-Yuan Wu ,  Chun-Hsiung Peng

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/42368

摘要： A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first field plate rings. The first conductive layer is electrically connected to the drain and at least one of the first field plate rings.

摘要翻译： 高压晶体管器件具有衬底，隔离结构，源极，栅极，漏极，多个掺杂区域，多个离子阱以及设置在衬底上的第一介电层。 高压晶体管器件还具有第一导电层和多个第一场板环。 第一导电层电连接到漏极和至少一个第一场板环。

公开(公告)号：US20070066062A1

公开(公告)日：2007-03-22

申请号：US11230346

申请日：2005-09-20

申请人： Te-Hsiang Liu ,  Chun-Hsiung Peng

发明人： Te-Hsiang Liu ,  Chun-Hsiung Peng

IPC分类号： B44C1/22 ,  H01L21/306 ,  H01L21/302

CPC分类号： H01J37/32623

摘要： A novel landing uniformity ring for an etch chamber is disclosed. The landing uniformity ring includes an annular ring body defining a ring opening and an increased-diameter inner flange extending inwardly from the ring body, into the ring opening. When mounted in a landing uniformity ring assembly, the inner flange is disposed at a horizontal gap distance with respect to the edge of the wafer which improves the flow efficiency of exhaust gases in the etch chamber. This prevents the accumulation of polymer residues on the assembly and reduces the incidence of particle-related defects in devices being fabricated on a wafer.

摘要翻译： 公开了一种用于蚀刻室的新型着色均匀性环。 着陆均匀环包括限定环形开口的环形环体和从环形体向内延伸到环形开口中的增大直径的内凸缘。 当安装在着陆均匀环组件中时，内凸缘相对于晶片的边缘设置在水平间隙距离处，这提高了蚀刻室中废气的流动效率。 这防止聚合物残余物在组件上的积聚并且减少在晶片上制造的器件中颗粒相关缺陷的发生率。