摘要:
A high-voltage semiconductor device is disclosed. The HV semiconductor device includes: a substrate; a well of first conductive type disposed in the substrate; a first doping region of second conductive type disposed in the p-well; a first isolation structure disposed in the well of first conductive type and surrounding the first doping region of second conductive type; and a first drift ring of second conductive type disposed between the first doping region of second conductive type and the first isolation structure.
摘要:
A high-voltage transistor device has a substrate, an isolation structure, a source, a gate, a drain, a plurality of doped regions, a plurality of ion wells, and a first dielectric layer disposed on the substrate. The high-voltage transistor device further has a first conductive layer and a plurality of first field plate rings. The first conductive layer is electrically connected to the drain and at least one of the first field plate rings.
摘要:
A method of fabricating a deep well region of a high voltage device is provided. The method includes designating a deep well region that includes a designated highly doped region and a designed scarcely doped region in a substrate. A mask layer, which covers a periphery of the designated deep well region, is formed over the substrate, wherein the mask layer includes a plurality of shielding parts to cover a portion of the designated scarcely doped region. Using the mask layer as an implantation mask, an ion implantation process is performed to implant dopants into the substrate exposed by the mask and to form a plurality of undoped regions in the designated scarcely doped region covered by the shielding parts. The dopants in the designated scarcely doped region are then induced to diffuse to the undoped regions.
摘要:
A phase grating image-sensing device. The device includes a plurality of photodiodes, a smoothing layer, a color filter layer and a plurality of phase gratings. The photodiodes are formed on a substrate and isolated from each other by isolation structures. The smoothing layer covers the photodiodes and the isolation structures. The color filter layer is embedded within the smoothing layer forming a sandwich structure with the smoothing layer. The phase gratings are formed over the smoothing layer positioned at corresponding locations above isolation structures. The phase grating layers produce a constructive interference of light passing through the smoothing layer.
摘要:
A connection method and a management server are provided. Each electronic apparatus detects connection behavior supported by a network, where the electronic apparatus is located, through the management server and accordingly generates a corresponding connection profile and stores it to the management server. The management server reads two connection profiles corresponding to two electronic apparatuses when the management server receives a connection request desired to connect from one of the electronic apparatuses to another one, and dynamically adjusts a plurality of connection detection procedures based on a connection success/failure record. The management server tests the connection detection procedures to determine whether a connection can be established between the two electronic apparatuses so as to obtain a session profile for establishing the connection.
摘要:
A method for fabricating a lateral-diffusion metal-oxide semiconductor (LDMOS) device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first region and a second region both having a first conductive type in the semiconductor substrate, wherein the first region not contacting the second region; and performing a thermal process to diffuse the dopants within the first region and the second region into the semiconductor substrate to form a deep well, wherein the doping concentration of the deep well is less than the doping concentration of the first region and the second region.
摘要:
A magnetic stack structure is disclosed. The magnetic stack structure includes two metal layers and a free layer sandwiched by the two metal layers. The thickness of the free layer is 1-30 nm. The thickness of the metal layers are 0.1-20 nm respectively.
摘要:
A method for operating a semiconductor device including a lateral double diffused metal oxide semiconductor (LDMOS) with a first source, a common drain and a first gate, a junction field effect transistor (JFET) with a second source, the common drain and a second gate wherein the second source is electrically connected to the first gate and an inner circuit electrically connected to the first source is provided. The first source provides the inner circuit with an inner current to generate an inner voltage by means of the lateral double diffused metal oxide semiconductor, and the lateral double diffused metal oxide semiconductor turns off when the inner voltage is elevated substantially as high as the first gate voltage.
摘要:
A semiconductor device includes a lateral double diffused metal oxide semiconductor (LDMOS) , a junction field effect transistor (JFET) and an inner circuit. The lateral double diffused metal oxide semiconductor includes a first source, a common drain and a first gate. The junction field effect transistor includes a second source, the common drain and a second gate. The second source is electrically connected to the first gate. The inner circuit is electrically connected to the first source.
摘要:
The present invention provides a method for forming capacitor of a dynamic random access memory cell. The method comprises providing a substrate and the word line structures formed thereon. A first dielectric layer is deposited on the substrate and the word line structures. A first polysilicon layer is deposited to form bit line contacts and bit lines. A second dielectric layer is formed on the first dielectric layer and the bit lines. The partial second dielectric layer is removed to form at least a wall structure in the second dielectric layer. The partial second dielectric layer and partial first dielectric layer are removed to form a capacitor contact opening. A second polysilicon is deposited into the capacitor contact opening and on the wall structure and the second dielectric layer. The partial second polysilicon is removed to form a capacitor node whereby a side-wall of the capacitor node is adjacent to the wall structure.