公开(公告)号：US20050276103A1

公开(公告)日：2005-12-15

申请号：US11143581

申请日：2005-06-03

申请人： Junichi Kato ,  Masayoshi Nakayama ,  Takao Ozeki ,  Asako Miyoshi ,  Shinichi Hatakeyama

发明人： Junichi Kato ,  Masayoshi Nakayama ,  Takao Ozeki ,  Asako Miyoshi ,  Shinichi Hatakeyama

IPC分类号： G11C11/34 ,  G11C14/00 ,  G11C16/04

CPC分类号： G11C14/00 ,  G11C16/0441

摘要： A switch section connects a first wire line aSL to the gate of a first memory transistor 1 and the source of a second memory transistor 2 and a second wire line bSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 when first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 and the second wire line bSL to the gate of the first memory transistor 1 and the source of the second memory transistor 2 when second type data is to be written into a memory cell.

摘要翻译： 开关部分将第一有线线路aSL连接到第一存储晶体管1的栅极和第二存储晶体管2的源极和第二有线线路bSL连接到第一存储晶体管1的源极和第二存储晶体管的栅极 当第一类数据被写入存储单元时; 并且将第一有线线路aSL连接到第一存储晶体管1的源极和第二存储晶体管2的栅极和第二有线线路bSL到第一存储晶体管1的栅极和第二存储晶体管2的源极， 第二类型数据将被写入存储单元。

公开(公告)号：US07161832B2

公开(公告)日：2007-01-09

申请号：US11143581

申请日：2005-06-03

申请人： Junichi Kato ,  Masayoshi Nakayama ,  Takao Ozeki ,  Asako Miyoshi ,  Shinichi Hatakeyama

发明人： Junichi Kato ,  Masayoshi Nakayama ,  Takao Ozeki ,  Asako Miyoshi ,  Shinichi Hatakeyama

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C14/00 ,  G11C16/0441

摘要： A switch section connects a first wire line aSL to the gate of a first memory transistor 1 and the source of a second memory transistor 2 and a second wire line bSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 when first type data is to be written into a memory cell; and connects the first wire line aSL to the source of the first memory transistor 1 and the gate of the second memory transistor 2 and the second wire line bSL to the gate of the first memory transistor 1 and the source of the second memory transistor 2 when second type data is to be written into a memory cell.

摘要翻译： 开关部分将第一有线线路aSL连接到第一存储晶体管1的栅极和第二存储晶体管2的源极和第二有线线路bSL连接到第一存储晶体管1的源极和第二存储晶体管的栅极 当第一类数据被写入存储单元时; 并且将第一有线线路aSL连接到第一存储晶体管1的源极和第二存储晶体管2的栅极和第二有线线路bSL到第一存储晶体管1的栅极和第二存储晶体管2的源极， 第二类型数据将被写入存储单元。

公开(公告)号：US08331157B2

公开(公告)日：2012-12-11

申请号：US13014360

申请日：2011-01-26

申请人： Takao Ozeki

发明人： Takao Ozeki

IPC分类号： G11C11/34

CPC分类号： G11C16/28 ,  G11C11/5642 ,  G11C2211/5634

摘要： First main bit lines correspond to at least one first memory cell. Second main bit lines correspond to at least one second memory cell. At least one sense amplifier outputs read data according to a difference between a voltage of any one of the first main bit lines and a voltage of any one of the second main bit lines. A voltage supply switching section supplies a predetermined reference voltage to one of the first main bit lines corresponding to one of the second main bit lines in which a current according to a threshold voltage of the at least one second memory cell is generated. A resistance switching section forms electrical connection between a ground node and the one of the second main bit lines in which the current according to the threshold voltage of the at least one second memory cell is generated with a predetermined resistance value.

摘要翻译： 第一主位线对应于至少一个第一存储单元。 第二主位线对应于至少一个第二存储单元。 至少一个读出放大器根据第一主位线中的任何一个的电压与任一个第二主位线的电压之差来输出读取数据。 电压供给切换部分将预定参考电压提供给与其中产生根据至少一个第二存储单元的阈值电压的电流相对应的第二主位线之一的第一主位线之一。 电阻切换部分形成接地节点与根据至少一个第二存储单元的阈值电压的电流之间的预定电阻值的第二主位线之一之间的电连接。

公开(公告)号：US20070118719A1

公开(公告)日：2007-05-24

申请号：US11595896

申请日：2006-11-13

申请人： Takao Ozeki ,  Makoto Arita ,  Kunisato Yamaoka ,  Shunichi Iwanari

发明人： Takao Ozeki ,  Makoto Arita ,  Kunisato Yamaoka ,  Shunichi Iwanari

IPC分类号： G06F12/00

CPC分类号： G06F12/1009 ,  G06F12/1408 ,  G06F2212/2022

摘要： There is provided a method for controlling a semiconductor memory which includes a memory cell array including a plurality of multivalued memory cells where, in each of the memory cells, a first write operation allows storage of data in a first page address and a second write operation allows storage of data in a second page address, the method comprising an address conversion table processing step and an address scramble step. At the address conversion table processing step, an address conversion table for address conversion is generated by, in each of the plurality of multivalued memory cells, allocating addresses in which writing is to be performed to addresses such that data is written in a second page address after writing of data in a first page address. At the address scramble step, address conversion is performed on an input address according to the address conversion table.

摘要翻译： 提供了一种用于控制半导体存储器的方法，其包括具有多个多值存储器单元的存储单元阵列，其中，在每个存储器单元中，第一写入操作允许将数据存储在第一页地址和第二写入操作 允许将数据存储在第二页地址中，该方法包括地址转换表处理步骤和地址加扰步骤。 在地址转换表处理步骤中，通过在多个多值存储器单元中的每一个中生成用于地址转换的地址转换表，分配要执行写入的地址以使得将数据写入第二页地址 在第一页地址写入数据之后。 在地址加扰步骤中，根据地址转换表对输入地址执行地址转换。

公开(公告)号：US07075839B2

公开(公告)日：2006-07-11

申请号：US10821983

申请日：2004-04-12

申请人： Toshio Mukunoki ,  Akira Sugimoto ,  Takao Ozeki

发明人： Toshio Mukunoki ,  Akira Sugimoto ,  Takao Ozeki

IPC分类号： G11C7/00

CPC分类号： G11C29/12 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/4402 ,  G11C2029/5004

摘要： A memory cell array includes a memory cell region composed of memory cells and a sample cell region composed of word line sample cells and bit line sample cells. The word line sample cell and the bit line sample cell are formed so that by a voltage applied to word lines and bit lines, charge transfer from the floating gate electrode occurs more easily than the memory cell.

摘要翻译： 存储单元阵列包括由存储单元组成的存储单元区域和由字线采样单元和位线采样单元组成的采样单元区域。 形成字线采样单元和位线采样单元，使得通过施加到字线和位线的电压，比浮动栅电极的电荷转移比存储单元更容易发生。

公开(公告)号：US06638015B2

公开(公告)日：2003-10-28

申请号：US10104001

申请日：2002-03-25

申请人： Yasuo Ozawa ,  Junya Yamamoto ,  Masaki Chujo ,  Takao Ozeki

发明人： Yasuo Ozawa ,  Junya Yamamoto ,  Masaki Chujo ,  Takao Ozeki

IPC分类号： F04D2912

CPC分类号： F01P5/10 ,  F01P2031/18 ,  F04D29/106 ,  F05B2260/603

摘要： A water pump apparatus includes a body adapted to a fixed mounting surface of an engine and having a bore, a rotational shaft rotatably supported on the body via a bearing, an impeller fixed to the shaft and located in a pump chamber for supplying forcibly water from a water inlet to a water outlet, a seal member for sealing between the pump chamber and the bore of the body and a collection chamber portion provided on at least one of the body or the engine so as to communicate with the bore between the bearing and the seal member via a drain passage and for collecting water leaked via the seal member, wherein the collection chamber portion is opened toward the mounting surface of the engine and an opening of the collection chamber portion is fluid-tight closed by fixing the body to the engine.