公开(公告)号：US20230156928A1

公开(公告)日：2023-05-18

申请号：US18157228

申请日：2023-01-20

Applicant: Juniper Networks, Inc.

Inventor： Steve WILKINSON ,  Daniel J. PREZIOSO

IPC: H05K3/42 ,  H05K3/22

CPC classification number: H05K3/425 ,  H05K3/22

Abstract: A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.

公开(公告)号：US20240379522A1

公开(公告)日：2024-11-14

申请号：US18314469

申请日：2023-05-09

Applicant: Juniper Networks, Inc.

Inventor： Leif HUTCHINSON ,  Daniel J. PREZIOSO ,  Boris REYNOV

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/36

Abstract: A semiconductor package includes a first substrate having a top surface and a bottom surface, and a second substrate having a top surface and a bottom surface. The bottom surface of the first substrate is connected to the top surface of the second substrate via at least one bonding layer. The first substrate includes one or more electrically conductive components arranged on the bottom surface of the first substrate in a first pattern. The second substrate includes one or more slots arranged on the bottom surface of the second substrate in a second pattern. The one or more slots are each plated with an electrically conductive material. The arrangement of the one or more electrically conductive components in the first pattern is aligned with the arrangement of the one or more slots in the second pattern. The second substrate includes a stiffener disposed within the second substrate.

公开(公告)号：US20210153359A1

公开(公告)日：2021-05-20

申请号：US17248569

申请日：2021-01-29

Applicant: Juniper Networks, Inc.

Inventor： Steve M. WILKINSON ,  Daniel J. PREZIOSO

IPC: H05K3/42 ,  H05K3/22

Abstract: A method may include obtaining a printed circuit board (PCB) that includes a set of vias that include a set of stub regions. The PCB may include a set of layers perpendicular to the set of vias. The set of layers may include a signal layer and a ground layer. The ground layer may be located between the set of stub regions and the signal layer. The method may include drilling to remove at least a portion of a stub region of a via of the set of vias. The method may include performing an electrical test to determine whether a sliver of conductive material is included within the via after drilling to remove the at least a portion of the stub region of the via.