公开(公告)号：US20240305376A1

公开(公告)日：2024-09-12

申请号：US18663749

申请日：2024-05-14

Applicant: Juniper Networks, Inc.

Inventor： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes ,  Jeffery J. Maki ,  Chul Soo Park ,  Yang Yue ,  Jon J. Anderson

IPC: H04B10/2581 ,  G02B6/42 ,  H01S5/40 ,  H04B10/40 ,  H04B10/50 ,  H04B10/516 ,  H04B10/60 ,  H04J14/04

CPC classification number: H04B10/2581 ,  G02B6/425 ,  H01S5/4062 ,  H04B10/40 ,  H04B10/503 ,  H04B10/5161 ,  H04B10/60 ,  H04J14/04

Abstract: A sourceless co-packaged optical-electrical chip can include a plurality of different optical transceivers, each of which can transmit to an external destination or internal components. Each of the transceivers can be configured for a different modulation format, such as different pulse amplitude, phase shift key, and quadrature amplitude modulation formats. Different light sources provide light for processing by the transceivers, where the light source and transceivers can be configured for different applications (e.g., different distances) and data rates. An optical coupler can combine the light for the different transceivers for input into the sourceless co-packaged optical-electrical chip via a polarization maintaining media (e.g., polarization maintaining few mode fiber and polarization maintaining single mode fiber), where another coupler operates in splitting mode to separate the different channels of light for the different transceivers according to different co-packaged configurations.

公开(公告)号：US20220103261A1

公开(公告)日：2022-03-31

申请号：US17478095

申请日：2021-09-17

Applicant: Juniper Networks, Inc.

Inventor： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes

IPC: H04B10/40 ,  H04L27/34 ,  H04L1/00

Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

公开(公告)号：US12267111B2

公开(公告)日：2025-04-01

申请号：US18197266

申请日：2023-05-15

Applicant: Juniper Networks, Inc.

Inventor： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes

IPC: H04B10/40 ,  H04L1/00 ,  H04L27/34

Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

公开(公告)号：US11901898B2

公开(公告)日：2024-02-13

申请号：US17817546

申请日：2022-08-04

Applicant: Juniper Networks, Inc.

Inventor： John Kenney ,  Bo Mi ,  Ryan Holmes

IPC: H03K21/40 ,  H01R13/66 ,  G01R31/3185

CPC classification number: H03K21/40 ,  H01R13/6675 ,  G01R31/318527

Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US11489528B1

公开(公告)日：2022-11-01

申请号：US17512682

申请日：2021-10-28

Applicant: Juniper Networks, Inc.

Inventor： John Kenney ,  Bo Mi ,  Ryan Holmes

IPC: H03K21/40 ,  H01R13/66 ,  G01R31/3185

Abstract: A disclosed apparatus for accomplishing such a task may include (1) a circuit board incorporated into a module designed for insertion into slots of computing devices, (2) at least one conductive contact disposed on the circuit board, (3) a counter circuit disposed on the circuit board and communicatively coupled to the conductive contact, wherein the counter circuit comprises (A) a signal-change detector that detects signal changes as the module is inserted into one of the slots of the computing devices and (B) a counter device that maintains a dynamic count indicative of a number of times that the module has been inserted into one of the slots of the computing devices based at least in part on the signal changes, (4) a battery electrically coupled to the counter circuit, wherein the battery powers the counter device prior to the insertion. Various other apparatuses, systems, and methods are also disclosed.

公开(公告)号：US11159238B1

公开(公告)日：2021-10-26

申请号：US16990348

申请日：2020-08-11

Applicant: Juniper Networks, Inc.

Inventor： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes ,  Jeffery J. Maki ,  Chul Soo Park ,  Yang Yue ,  Jon J. Anderson

IPC: H04B10/2581 ,  H01S5/40 ,  G02B6/42 ,  H04B10/60 ,  H04B10/50 ,  H04B10/516 ,  H04B10/40 ,  H04J14/04

Abstract: A sourceless co-packaged optical-electrical chip can include a plurality of different optical transceivers, each of which can transmit to an external destination or internal components. Each of the transceivers can be configured for a different modulation format, such as different pulse amplitude, phase shift key, and quadrature amplitude modulation formats. Different light sources provide light for processing by the transceivers, where the light source and transceivers can be configured for different applications (e.g., different distances) and data rates. An optical coupler can combine the light for the different transceivers for input into the sourceless co-packaged optical-electrical chip via a polarization maintaining media (e.g., polarization maintaining few mode fiber and polarization maintaining single mode fiber), where another coupler operates in splitting mode to separate the different channels of light for the different transceivers according to different co-packaged configurations.

公开(公告)号：US20230291478A1

公开(公告)日：2023-09-14

申请号：US18197266

申请日：2023-05-15

Applicant: Juniper Networks, Inc.

Inventor： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes

IPC: H04B10/40 ,  H04L1/00 ,  H04L27/34

CPC classification number: H04B10/40 ,  H04L1/0041 ,  H04L1/0045 ,  H04L27/34

Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

公开(公告)号：US11159240B1

公开(公告)日：2021-10-26

申请号：US17038453

申请日：2020-09-30

Applicant: Juniper Networks, Inc.

Inventor： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes

IPC: H04B10/40 ,  H04L27/34 ,  H04L1/00

Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

公开(公告)号：US20230254042A1

公开(公告)日：2023-08-10

申请号：US18130763

申请日：2023-04-04

Applicant: Juniper Networks, Inc.

Inventor： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes ,  Jeffrey J. Maki ,  Chul Soo Park ,  Yang Yue ,  Jon J. Anderson

IPC: H04B10/2581 ,  G02B6/42 ,  H01S5/40 ,  H04B10/40 ,  H04B10/50 ,  H04B10/516 ,  H04B10/60

CPC classification number: H04B10/2581 ,  G02B6/425 ,  H01S5/4062 ,  H04B10/40 ,  H04B10/503 ,  H04B10/5161 ,  H04B10/60 ,  H04J14/04

Abstract: A sourceless co-packaged optical-electrical chip can include a plurality of different optical transceivers, each of which can transmit to an external destination or internal components. Each of the transceivers can be configured for a different modulation format, such as different pulse amplitude, phase shift key, and quadrature amplitude modulation formats. Different light sources provide light for processing by the transceivers, where the light source and transceivers can be configured for different applications (e.g., different distances) and data rates. An optical coupler can combine the light for the different transceivers for input into the sourceless co-packaged optical-electrical chip via a polarization maintaining media (e.g., polarization maintaining few mode fiber and polarization maintaining single mode fiber), where another coupler operates in splitting mode to separate the different channels of light for the different transceivers according to different co-packaged configurations.

公开(公告)号：US11689289B2

公开(公告)日：2023-06-27

申请号：US17478095

申请日：2021-09-17

Applicant: Juniper Networks, Inc.

Inventor： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes

IPC: H04B10/40 ,  H04L1/00 ,  H04L27/34

CPC classification number: H04B10/40 ,  H04L1/0041 ,  H04L1/0045 ,  H04L27/34

Abstract: A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.