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    POWER EFFICIENT AND SCALABLE CO-PACKAGED OPTICAL DEVICES
    1.
    发明公开
    POWER EFFICIENT AND SCALABLE CO-PACKAGED OPTICAL DEVICES 审中-公开

    公开(公告)号：US20230291478A1

    公开(公告)日：2023-09-14

    申请号：US18197266

    申请日：2023-05-15

    申请人： Juniper Networks, Inc.

    发明人： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes

    IPC分类号： H04B10/40 ,  H04L1/00 ,  H04L27/34

    CPC分类号： H04B10/40 ,  H04L1/0041 ,  H04L1/0045 ,  H04L27/34

    摘要： A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

    Power efficient and scalable co-packaged optical devices
    2.
    发明授权
    Power efficient and scalable co-packaged optical devices 有权

    公开(公告)号：US11159240B1

    公开(公告)日：2021-10-26

    申请号：US17038453

    申请日：2020-09-30

    申请人： Juniper Networks, Inc.

    发明人： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes

    IPC分类号： H04B10/40 ,  H04L27/34 ,  H04L1/00

    摘要： A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

    External laser enabled co-packaged optics architectures
    3.
    发明授权
    External laser enabled co-packaged optics architectures 有权

    公开(公告)号：US11159238B1

    公开(公告)日：2021-10-26

    申请号：US16990348

    申请日：2020-08-11

    申请人： Juniper Networks, Inc.

    发明人： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes ,  Jeffery J. Maki ,  Chul Soo Park ,  Yang Yue ,  Jon J. Anderson

    IPC分类号： H04B10/2581 ,  H01S5/40 ,  G02B6/42 ,  H04B10/60 ,  H04B10/50 ,  H04B10/516 ,  H04B10/40 ,  H04J14/04

    摘要： A sourceless co-packaged optical-electrical chip can include a plurality of different optical transceivers, each of which can transmit to an external destination or internal components. Each of the transceivers can be configured for a different modulation format, such as different pulse amplitude, phase shift key, and quadrature amplitude modulation formats. Different light sources provide light for processing by the transceivers, where the light source and transceivers can be configured for different applications (e.g., different distances) and data rates. An optical coupler can combine the light for the different transceivers for input into the sourceless co-packaged optical-electrical chip via a polarization maintaining media (e.g., polarization maintaining few mode fiber and polarization maintaining single mode fiber), where another coupler operates in splitting mode to separate the different channels of light for the different transceivers according to different co-packaged configurations.

    Packet routing using optical supervisory channel data for an optical transport system
    4.
    发明授权
    Packet routing using optical supervisory channel data for an optical transport system 有权

    公开(公告)号：US10284290B2

    公开(公告)日：2019-05-07

    申请号：US14871586

    申请日：2015-09-30

    申请人： Juniper Networks, Inc.

    发明人： Gert Grammel ,  Domenico Di Mola ,  Steven B. Alleston

    IPC分类号： H04B10/038 ,  H04B10/077 ,  H04L12/24 ,  H04L12/707 ,  H04Q11/00 ,  H04J14/02

    摘要： In some examples, a network device comprises one or more processors operably coupled to a memory, and a routing unit configured for execution by the one or more processors to route data traffic on a layer 3 network overlaying an optical transport system; receive optical supervisory channel data for an optical supervisory channel of the optical transport system; determine the optical supervisory channel data indicates an event affecting transmission or detection of a signal transported by a wavelength, the wavelength traversing an optical fiber of the optical transport system and underlying a link of the layer 3 network; and reconfigure, in response to determining the optical supervisory channel data indicates the event, a configuration of the network device to modify routing operations of the network device with respect to the data traffic on the layer 3 network.

    POWER EFFICIENT AND SCALABLE CO-PACKAGED OPTICAL DEVICES
    7.
    发明申请
    POWER EFFICIENT AND SCALABLE CO-PACKAGED OPTICAL DEVICES 有权

    公开(公告)号：US20220103261A1

    公开(公告)日：2022-03-31

    申请号：US17478095

    申请日：2021-09-17

    申请人： Juniper Networks, Inc.

    发明人： Domenico Di Mola ,  Steven B. Alleston ,  Zhen Qu ,  Ryan Holmes

    IPC分类号： H04B10/40 ,  H04L27/34 ,  H04L1/00

    摘要： A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.

    NETWORK TOPOLOGY OPTIMIZATION WITH FEASIBLE OPTICAL PATHS
    9.
    发明申请
    NETWORK TOPOLOGY OPTIMIZATION WITH FEASIBLE OPTICAL PATHS 有权
    网络拓扑优化与可行光学PATHS

    公开(公告)号：US20160191194A1

    公开(公告)日：2016-06-30

    申请号：US14788602

    申请日：2015-06-30

    申请人： Juniper Networks, Inc.

    发明人： David C. Wood ,  Massimiliano Salsi ,  Steven B. Alleston

    IPC分类号： H04J14/02 ,  H04B10/27

    CPC分类号： H04J14/0286 ,  H04B10/27 ,  H04J14/0267 ,  H04J2203/0055 ,  H04J2203/0098 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/14

    摘要： In general, techniques are described for dynamically determining a logical network topology for more efficiently transporting network traffic over a physical topology based on end-to-end network traffic demands and optical transport network (OTN) characteristics of the network. The techniques may be applicable to meeting network traffic demands placed upon a multi-layer network having a base transport layer and a logical or overlay Internet Protocol (IP) layer routed on the transport layer.

    摘要翻译： 一般来说，描述了基于网络的端到端网络业务需求和光传送网络（OTN）特性来动态地确定逻辑网络拓扑以更有效地传输物理拓扑上的网络业务的技术。 这些技术可以适用于满足具有在传输层上路由的基本传输层和逻辑或覆盖因特网协议（IP）层的多层网络的网络流量需求。