公开(公告)号：US08486788B2

公开(公告)日：2013-07-16

申请号：US13162310

申请日：2011-06-16

申请人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US20110244645A1

公开(公告)日：2011-10-06

申请号：US13162310

申请日：2011-06-16

申请人： Junko IWANAGA ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko IWANAGA ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US07986002B2

公开(公告)日：2011-07-26

申请号：US10549291

申请日：2004-03-19

申请人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L29/66

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US20060208300A1

公开(公告)日：2006-09-21

申请号：US10549291

申请日：2004-03-19

申请人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

发明人： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC分类号： H01L27/108

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

摘要： A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

摘要翻译： 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US07473967B2

公开(公告)日：2009-01-06

申请号：US10558671

申请日：2004-05-31

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

摘要翻译： 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由连接部的长度方向的至少一部分形成的通道区域（15a）; 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US20070052041A1

公开(公告)日：2007-03-08

申请号：US10558671

申请日：2004-05-31

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC分类号： H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

摘要翻译： 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由所述连接部的至少一部分在所述连接部的长度方向上形成的通路区域（15a） 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US06852602B2

公开(公告)日：2005-02-08

申请号：US10298000

申请日：2002-01-30

申请人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Yoshihiro Hara ,  Takeshi Takagi ,  Takahiro Kawashima

发明人： Yoshihiko Kanzawa ,  Tohru Saitoh ,  Katsuya Nozawa ,  Minoru Kubo ,  Yoshihiro Hara ,  Takeshi Takagi ,  Takahiro Kawashima

IPC分类号： H01L21/205 ,  H01L29/15 ,  H01L29/24 ,  H01L29/737 ,  H01L29/80 ,  H01L21/331

CPC分类号： H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02661 ,  H01L29/155 ,  H01L29/1608 ,  H01L29/7378 ,  H01L29/802

摘要： A multi-layer film 10 is formed by stacking a Si1-x1-y1Gex1Cy1 layer (0≦x1 y2) having a high Ge mole fraction, e.g., a Si0.2Ge0.8 layer 12. In this manner, the range in which the multi-layer film serves as a SiGeC layer with C atoms incorporated into lattice sites extends to high degrees in which a Ge mole fraction is high.

摘要翻译： 通过层叠具有小Ge摩尔分数的Si1-x1-y1Gex1Cy1层（0 <= x1 <1和0 y2），例如Si0.2Ge0.8层 以这种方式，多层膜用作结合到晶格点中的C原子的SiGeC层的范围延伸到Ge摩尔分数高的高度。

公开(公告)号：US20070085167A1

公开(公告)日：2007-04-19

申请号：US10564085

申请日：2004-07-06

申请人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

发明人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

IPC分类号： H01L27/082

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.

摘要翻译： 双极晶体管120包括衬底1，本征基极区域11和外部基极区域12。 本征基极区域11包括由衬底1上形成的硅构成的硅缓冲层109和形成在硅缓冲层上并包含硅和至少锗的组成比梯度的基底层111，其中组成 锗与硅的比例在组成比梯度的基底层111的厚度方向上变化。 外部基极区域12包括由硅构成的非本征基底形成层113，其形成在衬底上并与硅缓冲层相邻。 外部基底形成层113的厚度不小于40nm。

公开(公告)号：US07719031B2

公开(公告)日：2010-05-18

申请号：US10564085

申请日：2004-07-06

申请人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

发明人： Tohru Saitoh ,  Takahiro Kawashima ,  Ken Idota ,  Yoshihiko Kanzawa ,  Teruhito Ohnishi

IPC分类号： H01L29/74

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.

摘要翻译： 双极晶体管120包括衬底1，本征基极区域11和非本征基极区域12.本征基极区域11包括由衬底1上形成的硅构成的硅缓冲层109和组成比分级基底 层111，其形成在硅缓冲层上并且包含硅并且至少为锗，并且其中锗与硅的组成比在组成比梯度基底层111的厚度方向上变化。外部基极区12包括 外部基底形成层113由硅构成，其形成在衬底上并与硅缓冲层相邻。 外部基底形成层113的厚度不小于40nm。

公开(公告)号：US06399993B1

公开(公告)日：2002-06-04

申请号：US09786551

申请日：2001-03-07

申请人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

发明人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

IPC分类号： H01L2972

CPC分类号： H01L21/76237 ,  H01L21/8249

摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.

摘要翻译： 在双极晶体管块中，SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）依次层叠在集电极扩散层（9）上。 在基底层（20a）的两个边缘上设置有由多晶硅制成的基底底涂层绝缘膜（5a）和基底延伸电极（22）。 基底层（20a）具有与基底底涂层绝缘膜（5a）的厚度相等的周边部分和比周边部分厚的中心部分。 用于CMOS块的基底涂层绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。 由于作为基底层的SiGe层与基底底涂层绝缘膜5a之间的热膨胀系数的差异导致的应力可以降低，并且实现了高可靠性的BiCMOS器件。