公开(公告)号：US20240202111A1

公开(公告)日：2024-06-20

申请号：US18461374

申请日：2023-09-05

Applicant: Kioxia Corporation

Inventor： Haruka MORI ,  Mitsunori TADOKORO ,  Akinori NAGAOKA

IPC: G06F12/02 ,  G11C29/52

CPC classification number: G06F12/0238 ,  G11C29/52

Abstract: According to one embodiment, a controller for a memory system including a nonvolatile memory with physical blocks sets logical blocks including the physical blocks, manages a first table having a first value indicating a threshold voltage to be used for reading data from each logical block, a second table for each physical block having a corrected threshold voltage that has been statistically determined to be an outlier in association with a second value indicating the corrected threshold voltage for the physical block. The controller performs a threshold voltage tracking for identifying a threshold voltage suitable for reading data from a physical block if a reading fails, and then retries the reading using the threshold voltage obtained by the threshold voltage tracking. The controller updates the first table if the physical block is not listed in the second table, but not otherwise.

公开(公告)号：US20210294740A1

公开(公告)日：2021-09-23

申请号：US17009694

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Akinori NAGAOKA ,  Mitsunori TADOKORO

IPC: G06F12/02 ,  G06F11/10

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

公开(公告)号：US20230136654A1

公开(公告)日：2023-05-04

申请号：US17903049

申请日：2022-09-06

Applicant: KIOXIA CORPORATION

Inventor： Haruka MORI ,  Mitsunori TADOKORO ,  Akinori NAGAOKA

IPC: G06F3/06

Abstract: A memory system includes a non-volatile memory including first and second memory chips connected to a channel, each chip outputting a first signal indicating whether the chip is in a busy state, a first queue storing commands to be executed by the first chip, a second queue storing commands to be executed by the second chip, a processor configured to issue a second signal indicating whether a command in the first or second queue is a first-type or a second-type command, the first-type command causing the first or second chip to be in the busy state longer than the second-type command, a first arbiter selecting from the first and second queues a command to be executed next based on the first and second signals, and an interface controller sending the selected command via the channel to the first or second memory chip.

公开(公告)号：US20230122919A1

公开(公告)日：2023-04-20

申请号：US18084407

申请日：2022-12-19

Applicant: KIOXIA CORPORATION

Inventor： Akinori NAGAOKA ,  Mitsunori TADOKORO

IPC: G06F12/02 ,  G06F11/10

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.