公开(公告)号：US20210294740A1

公开(公告)日：2021-09-23

申请号：US17009694

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Akinori NAGAOKA ,  Mitsunori TADOKORO

IPC: G06F12/02 ,  G06F11/10

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

公开(公告)号：US20210294506A1

公开(公告)日：2021-09-23

申请号：US17009068

申请日：2020-09-01

Applicant: Kioxia Corporation

Inventor： Mitsunori TADOKORO

IPC: G06F3/06

Abstract: According to one embodiment, a memory system allocates one or more areas of a plurality of areas obtained by equally dividing a first logical address space of the memory system to each of a plurality of namespaces. Each of the areas has such a size that areas corresponding in number to a maximum number of namespaces to be supported are allocable to a remaining space excluding a size equivalent to that of an advertised capacity form the first logical address space. When a size of a first namespace is to be expanded, the memory system updates the first management table and additionally allocates an unused area to the first namespace.

公开(公告)号：US20230185708A1

公开(公告)日：2023-06-15

申请号：US17841444

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Toru MOTOYA ,  Mitsunori TADOKORO ,  Tomonori YOKOYAMA ,  Fuyuki ICHIBA ,  Kensuke MINATO ,  Kimihisa OKA

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0679 ,  G06F3/0643 ,  G06F3/0604 ,  G06F2212/7207

Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

公开(公告)号：US20230136654A1

公开(公告)日：2023-05-04

申请号：US17903049

申请日：2022-09-06

Applicant: KIOXIA CORPORATION

Inventor： Haruka MORI ,  Mitsunori TADOKORO ,  Akinori NAGAOKA

IPC: G06F3/06

Abstract: A memory system includes a non-volatile memory including first and second memory chips connected to a channel, each chip outputting a first signal indicating whether the chip is in a busy state, a first queue storing commands to be executed by the first chip, a second queue storing commands to be executed by the second chip, a processor configured to issue a second signal indicating whether a command in the first or second queue is a first-type or a second-type command, the first-type command causing the first or second chip to be in the busy state longer than the second-type command, a first arbiter selecting from the first and second queues a command to be executed next based on the first and second signals, and an interface controller sending the selected command via the channel to the first or second memory chip.

公开(公告)号：US20230122919A1

公开(公告)日：2023-04-20

申请号：US18084407

申请日：2022-12-19

Applicant: KIOXIA CORPORATION

Inventor： Akinori NAGAOKA ,  Mitsunori TADOKORO

IPC: G06F12/02 ,  G06F11/10

Abstract: A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.

公开(公告)号：US20250094055A1

公开(公告)日：2025-03-20

申请号：US18799619

申请日：2024-08-09

Applicant: Kioxia Corporation

Inventor： Kenta INAKAGATA ,  Mitsunori TADOKORO

IPC: G06F3/06

Abstract: A controller of a memory system issues a first memory read request for reading first data at a head of data to be read from a first memory die to the first memory die. When remaining data following the first data is included in the data to be read, the controller transfers a first identifier from a first command queue to a second command queue corresponding to a second memory die in which second data at a head of the remaining data is stored. The controller issues a second memory read request for reading the second data from the second memory die to the second memory die in response to transferring the first identifier to the second command queue.

公开(公告)号：US20230305705A1

公开(公告)日：2023-09-28

申请号：US17901837

申请日：2022-09-01

Applicant: KIOXIA CORPORATION

Inventor： Mitsunori TADOKORO

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0679 ,  G06F3/0659

Abstract: A memory system includes a non-volatile memory including first and second chips, a processor configured to generate first messages in response to a command from an external device, the first messages addressed to the first and second chips, and a repeater including an input port to which the first messages are input and first and second output ports connected to the first and second chips. The repeater is configured to write the first messages input via the input port to a shared memory, read the first message addressed to the first chip from the shared memory when the first chip is ready, and output the first message to the first chip through the first output port, and read the first message addressed to the second chip when the second chip is ready, and output the second message to the second chip through the second output port.

公开(公告)号：US20220300424A1

公开(公告)日：2022-09-22

申请号：US17472402

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Mitsunori TADOKORO

IPC: G06F12/0864 ,  G06F3/06

Abstract: A memory system according to an embodiment includes a first memory, a second memory, and a controller. The first memory stores first information that associates each of logical addresses indicating positions in a logical address space with a corresponding one of physical addresses indicating physical positions in the first memory. The second memory includes a cache area storing second information that is a part of the first information. The controller includes a first circuit controlling access to the first memory and a second circuit controlling access to the second memory. When cache miss occurs, the controller executes first processing of transmitting a first request for preparation of a cache entry of the second information to the first circuit and second processing of providing a second request regarding the cache entry to the second circuit in response to reception of notification indicating completion of the preparation of the cache entry.

公开(公告)号：US20210294738A1

公开(公告)日：2021-09-23

申请号：US17008529

申请日：2020-08-31

Applicant: KIOXIA CORPORATION

Inventor： Mitsunori TADOKORO

IPC: G06F12/02 ,  G06F12/0871 ,  G06F12/0831 ,  G06F13/16

Abstract: A storage apparatus includes a storage device that stores a table mapping a logical address to a physical address and a controller that manages the table and controls write of data to and read of data from the storage device according to a request from a host. The controller allocates, in a memory, a cache area for temporarily storing a part of the table, and a write buffer area for storing a part of the table that has been updated by the host and is to be written to the storage device, upon receipt of a request that requires update of the table from the host, determines whether a first part of the table to be updated is in the write buffer area, and upon determining that the first part is in the write buffer area, updates the first part in the write buffer area according to the request.

公开(公告)号：US20240311039A1

公开(公告)日：2024-09-19

申请号：US18586342

申请日：2024-02-23

Applicant: Kioxia Corporation

Inventor： Haruka MORI ,  Mitsunori TADOKORO

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory system includes a plurality of memory chips, a memory, and a controller. The memory chips are capable of operating in parallel. The memory includes a physical channel region and a plurality of virtual channel regions, each corresponding to one of a plurality of processes executed on the memory chips according to the requests. The controller stores the requests issued from the host in the physical channel region in order of acquisition from the host, and an entry for each of the requests in one of the virtual channel regions. When a required degree of parallelism of the processes is less than a threshold, the controller selects a next request to be executed using the physical channel region. When the required degree of parallelism is greater than or equal to the threshold, the controller selects a next request to be executed using one of the virtual channel regions.