公开(公告)号：US10910068B2

公开(公告)日：2021-02-02

申请号：US16727488

申请日：2019-12-26

Applicant: KIOXIA Corporation

Inventor： Kazutaka Takizawa ,  Yoshihisa Kojima ,  Masaaki Niijima

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/22 ,  H01L27/11582 ,  G11C11/56 ,  H01L27/11556

Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory cells at intersection locations of stacked word lines and a memory pillar passing through the word lines in a stacking direction, the word lines including a first group of word lines stacked above a second group of word lines. The controller reads data of a first memory cell in a first read mode and reads data of a second memory cell in a second read mode. The first memory cell is, and the second memory cell is not, at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar. The boundary area is adjacent to a location of the memory pillar where a width of the memory pillar discontinuously changes along the stacking direction.

公开(公告)号：US11410735B2

公开(公告)日：2022-08-09

申请号：US17038721

申请日：2020-09-30

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka Takizawa ,  Yoshihisa Kojima ,  Masaaki Niijima

IPC: G11C16/14 ,  G11C16/26 ,  G11C7/04 ,  G11C16/32 ,  G11C16/34 ,  G11C16/30

Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.

公开(公告)号：US11127476B2

公开(公告)日：2021-09-21

申请号：US16817371

申请日：2020-03-12

Applicant: Kioxia Corporation

Inventor： Kazutaka Takizawa ,  Yoshihisa Kojima ,  Sumio Kuroda ,  Masaaki Niijima

IPC: G11C16/34 ,  G11C29/44 ,  G11C16/14 ,  G11C16/12 ,  G11C16/26

Abstract: According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage.