公开(公告)号：US20230395167A1

公开(公告)日：2023-12-07

申请号：US18179505

申请日：2023-03-07

Applicant: Kioxia Corporation

Inventor： Takumi FUJIMORI ,  Tetsuya SUNATA ,  Masanobu SHIRAKAWA ,  Hidehiro SHIGA

IPC: G11C16/34 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/16

Abstract: According to an embodiment, a memory system includes: a nonvolatile memory including a plurality of blocks; and a memory controller. The memory controller is configured to: make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to a first block targeted for erasure; cause the nonvolatile memory to execute a erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and cause the nonvolatile memory to execute a erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period.

公开(公告)号：US20230161492A1

公开(公告)日：2023-05-25

申请号：US18089904

申请日：2022-12-28

Applicant: Kioxia Corporation

Inventor： Takahiro KURITA ,  Tetsuya SUNATA ,  Shinichi KANNO

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0679 ,  G06F3/0659 ,  G06F3/0604

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.

公开(公告)号：US20210405900A1

公开(公告)日：2021-12-30

申请号：US17201559

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Takahiro KURITA ,  Tetsuya SUNATA ,  Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.

公开(公告)号：US20230090202A1

公开(公告)日：2023-03-23

申请号：US17686148

申请日：2022-03-03

Applicant: KIOXIA CORPORATION

Inventor： Takumi FUJIMORI ,  Tetsuya SUNATA ,  Masanobu SHIRAKAWA ,  Hideki YAMADA

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34

Abstract: A memory device includes a first block including a first memory cell and a first word line connected to the first memory cell, a second block including a second memory cell and a second word line connected to the second memory cell, and a control circuit. The control circuit applies a first voltage to each of the first and second word lines to supply a first erase pulse having a first erase intensity to each of the first and second blocks, when a first erase operation is executed, and applies the first voltage to the first word line and a second voltage higher than the first voltage to the second word line, to supply the first erase pulse to the first block and a second erase pulse having a second erase intensity less than the first erase intensity to the second block, when a second erase operation is executed.

公开(公告)号：US20230089083A1

公开(公告)日：2023-03-23

申请号：US17684576

申请日：2022-03-02

Applicant: Kioxia Corporation

Inventor： Reina NISHINO ,  Tetsuya SUNATA ,  Takumi FUJIMORI

IPC: G06F12/02 ,  G06F3/06

Abstract: A memory system includes a memory and a controller. The memory is configured to store a number of valid data in each of a plurality of logical blocks and a number of valid data for each of a plurality of banks in each of the logical blocks. The controller is configured to: select logical blocks of garbage collection target candidates based on the numbers of valid data in the logical blocks; calculate a maximum value among the numbers of valid data for the banks in each of the logical blocks of the garbage collection target candidates as a respective comparison value; and select one of the logical blocks of the garbage collection targets based on comparing the respective comparison values of the logical blocks of the garbage collection target candidates with each other.

公开(公告)号：US20220300204A1

公开(公告)日：2022-09-22

申请号：US17410789

申请日：2021-08-24

Applicant: Kioxia Corporation

Inventor： Tetsuya SUNATA ,  Takumi FUJIMORI ,  Takahiro KURITA

IPC: G06F3/06

Abstract: A memory system includes a nonvolatile memory, a volatile memory, and a memory controller. The volatile memory includes a write buffer. The memory controller receives commands stored in a queue by a host device from the queue. The memory controller receives a command stored in a queue by the host device from the queue and, in a state where first data not satisfying a write unit is stored in the write buffer, when receiving a first command for writing the first data to the nonvolatile memory from the queue, simultaneously writes the first data and second data acquired from the host device or a predetermined region of the volatile memory different from the write buffer to the nonvolatile memory.

公开(公告)号：US20230244397A1

公开(公告)日：2023-08-03

申请号：US17897071

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Takumi FUJIMORI ,  Tetsuya SUNATA

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0658 ,  G06F3/0652 ,  G06F3/0679

Abstract: A memory system includes a nonvolatile memory including blocks, and a memory controller. The memory controller is configured to set each of the blocks to be in one of a plurality of states, including first, second, third, and fourth states. The memory controller is configured to detect a predetermined condition related to at least one of an amount of data being written into blocks in the first state and state transition of a block, upon detection of the predetermined condition, determine a maximum number of blocks to be in the fourth state based on a length of time during which each block in the fourth state has been in the fourth state, and perform an erase operation to cause one or more blocks in the third state to transition to the fourth state when a current number of blocks in the fourth state is less than the maximum number.