公开(公告)号：US20240312519A1

公开(公告)日：2024-09-19

申请号：US18666886

申请日：2024-05-17

Applicant: KIOXIA CORPORATION

Inventor： Tomonori TAKAHASHI ,  Masanobu SHIRAKAWA ,  Osamu TORII ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

公开(公告)号：US20220270678A1

公开(公告)日：2022-08-25

申请号：US17738069

申请日：2022-05-06

Applicant: KIOXIA CORPORATION

Inventor： Tomonori TAKAHASHI ,  Masanobu SHIRAKAWA ,  Osamu TORII ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

公开(公告)号：US20230290407A1

公开(公告)日：2023-09-14

申请号：US18321338

申请日：2023-05-22

Applicant: KIOXIA CORPORATION

Inventor： Tomonori TAKAHASHI ,  Masanobu SHIRAKAWA ,  Osamu TORII ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C11/5671 ,  G11C16/26 ,  G11C16/08 ,  G11C16/0483

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.