公开(公告)号：US20240365540A1

公开(公告)日：2024-10-31

申请号：US18771585

申请日：2024-07-12

Applicant: Kioxia Corporation

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H10B41/27 ,  H01L21/74 ,  H01L21/768 ,  H01L23/535 ,  H01L25/00 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/27 ,  H01L21/743 ,  H01L21/76889 ,  H01L23/535 ,  H01L25/00 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H01L2924/0002

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.

公开(公告)号：US20220246631A1

公开(公告)日：2022-08-04

申请号：US17726081

申请日：2022-04-21

Applicant: KIOXIA CORPORATION

Inventor： Yoshihiro AKUTSU ,  Ryota KATSUMATA

IPC: H01L27/11556 ,  H01L21/768 ,  H01L21/74 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11578 ,  H01L23/535 ,  H01L27/11573 ,  H01L25/00

Abstract: This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer.