公开(公告)号：US09779202B2

公开(公告)日：2017-10-03

申请号：US14867226

申请日：2015-09-28

Applicant: KLA-Tencor Corporation

Inventor： Pradeep Vukkadala ,  Jaydeep Sinha ,  Jong-Hoon Kim

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/44

CPC classification number: G06F17/5081 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70633 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

公开(公告)号：US20160371423A1

公开(公告)日：2016-12-22

申请号：US14867226

申请日：2015-09-28

Applicant: KLA-Tencor Corporation

Inventor： Pradeep Vukkadala ,  Jaydeep Sinha ,  Jong-Hoon Kim

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/44 ,  G03F7/705 ,  G03F7/70633 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: Systems and methods to detect, quantify, and control process-induced asymmetric signatures using patterned wafer geometry measurements are disclosed. The system may include a geometry measurement tool configured to obtain a first set of wafer geometry measurements of the wafer prior to the wafer undergoing a fabrication process and to obtain a second set of wafer geometry measurements of the wafer after the fabrication process. The system may also include a processor in communication with the geometry measurement tool. The processor may be configured to: calculate a geometry-change map based on the first set of wafer geometry measurements and the second set of wafer geometry measurements; analyze the geometry-change map to detect an asymmetric component induced to wafer geometry by the fabrication process; and estimate an asymmetric overlay error induced by the fabrication process based on the asymmetric component detected in wafer geometry.

Abstract translation: 公开了使用图案化晶片几何测量来检测，量化和控制过程诱导的不对称签名的系统和方法。 该系统可以包括几何测量工具，其被配置成在晶片经历制造工艺之前获得晶片的第一组晶片几何测量，并且在制造工艺之后获得晶片的第二组晶片几何测量。 系统还可以包括与几何测量工具通信的处理器。 处理器可以被配置为：基于第一组晶片几何测量和第二组晶片几何测量来计算几何变化图; 分析几何变化图以通过制造过程检测诱导到晶片几何的不对称分量; 并且基于在晶片几何中检测到的不对称分量来估计由制造工艺引起的不对称重叠误差。