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    Method and apparatus for accelerating GNN pre-processing
    2.
    发明授权
    Method and apparatus for accelerating GNN pre-processing 有权

    公开(公告)号：US12248814B2

    公开(公告)日：2025-03-11

    申请号：US18453702

    申请日：2023-08-22

    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

    Inventor： Myoungsoo Jung ,  Seungkwan Kang ,  Donghyun Gouk ,  Miryeong Kwon ,  Hyunkyu Choi ,  Junhyeok Jang

    IPC: G06F7/76 ,  G06F7/36 ,  G06F9/50

    Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.

    NON-VOLATILE MEMORY CONTROLLER DEVICE AND NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    NON-VOLATILE MEMORY CONTROLLER DEVICE AND NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20220027295A1

    公开(公告)日：2022-01-27

    申请号：US17382895

    申请日：2021-07-22

    Applicant: MemRay Corporation ,  Korea Advanced Institute of Science and Technology

    Inventor： Myoungsoo Jung

    IPC: G06F13/16 ,  G06F13/42 ,  G06F13/28

    Abstract: In a non-volatile memory controlling device, a first doorbell region is exposed to a configuration space of a host interface and updated when the host issues an input/output (I/O) request command to the host memory. A fetch managing module fetches the command from the host memory in response to an event signal generated when the first doorbell region is updated. A data transferring module checks a location of the host memory based on request information included in the command, and performs a transfer of target data for the I/O request between the host memory and the non-volatile memory module. A completion handling module writes a completion request in the host memory and handles an interrupt when the data transferring module completes to process the I/O request. A second doorbell region is exposed to the configuration space and updated when the I/O service is terminated by the host.

    Hybrid memory system and accelerator including the same
    6.
    发明授权
    Hybrid memory system and accelerator including the same 有权

    公开(公告)号：US12210744B2

    公开(公告)日：2025-01-28

    申请号：US18090645

    申请日：2022-12-29

    Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

    Inventor： Myoungsoo Jung ,  Jie Zhang ,  Hanyeoreum Bae

    IPC: G06F12/00 ,  G06F3/06

    Abstract: An accelerator includes a processor and a hybrid memory system. The hybrid memory system includes a resistance-based non-volatile memory, a DRAM used as a cache of the resistance-based non-volatile memory, a non-volatile memory controller connected to the resistance-based non-volatile memory and configured to control the DRAM and the resistance-based non-volatile memory, a memory controller configured to process a memory request from the processor and control the DRAM, and a memory channel configured to connect the DRAM, the non-volatile memory controller, and the memory controller.

    Non-volatile memory controller device and non-volatile memory device
    8.
    发明授权
    Non-volatile memory controller device and non-volatile memory device 有权

    公开(公告)号：US11775452B2

    公开(公告)日：2023-10-03

    申请号：US17382895

    申请日：2021-07-22

    Applicant: MemRay Corporation ,  Korea Advanced Institute of Science and Technology

    Inventor： Myoungsoo Jung

    IPC: G06F13/16 ,  G06F13/28 ,  G06F13/42

    CPC classification number: G06F13/1668 ,  G06F13/28 ,  G06F13/4282 ,  G06F2213/0026

    Abstract: In a non-volatile memory controlling device, a first doorbell region is exposed to a configuration space of a host interface and updated when the host issues an input/output (I/O) request command to the host memory. A fetch managing module fetches the command from the host memory in response to an event signal generated when the first doorbell region is updated. A data transferring module checks a location of the host memory based on request information included in the command, and performs a transfer of target data for the I/O request between the host memory and the non-volatile memory module. A completion handling module writes a completion request in the host memory and handles an interrupt when the data transferring module completes to process the I/O request. A second doorbell region is exposed to the configuration space and updated when the I/O service is terminated by the host.

    STORAGE CARD AND STORAGE DEVICE
    10.
    发明申请
    STORAGE CARD AND STORAGE DEVICE 有权

    公开(公告)号：US20220027294A1

    公开(公告)日：2022-01-27

    申请号：US17382863

    申请日：2021-07-22

    Applicant: MemRay Corporation ,  Korea Advanced Institute of Science and Technology

    Inventor： Myoungsoo Jung ,  Gyuyoung Park

    IPC: G06F13/16 ,  G06F13/42

    Abstract: In a storage card, a first module exposes a set of registers including a first register to the host through a configuration space of a host interface, and the first register is written when the host submits a command of an I/O request to the host memory. A second module fetches the command from the host memory when the first register is written. A third module detects a location of the host memory based on a host memory address of request information in response to signaling of the second module, and performs a transfer of target data between the host memory and a memory controller. A fourth module writes a completion event to the host memory through the configuration space in response to service completion of the I/O request in the third module, and informs the host about I/O completion by writing an interrupt.

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