公开(公告)号：US11082032B2

公开(公告)日：2021-08-03

申请号：US16801432

申请日：2020-02-26

申请人： KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY ,  KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, SEJONG CAMPUS

发明人： Jungwon Kim ,  Hayun Cecillia Chung ,  Minji Hyun ,  Yongjin Na

IPC分类号： H03K3/42 ,  G01J1/04 ,  G01J1/42 ,  G01J1/46 ,  G06F1/04 ,  G01J1/44

摘要： A low-jitter digital clock signal generating system which uses optical pulses output from a pulse laser includes a first balanced photodetector that converts first and second optical pulses with a delayed time interval into first and second electrical pulses through first and second photodiodes and outputs first and second modulated pulses generated by allowing the first and second electrical pulses to partially overlap each other, a second balanced photodetector that converts third and fourth optical pulses with the delayed time interval into third and fourth electrical pulses through third and fourth photodiodes, and outputs a second modulated pulse generated by allowing the third and fourth electrical pulses to partially overlap each other, and a capacitor. The capacitor is charged by the first modulated pulse, is discharged by the second modulated pulse, and outputs a voltage according to the charging and discharging as a clock signal.

公开(公告)号：US09998302B2

公开(公告)日：2018-06-12

申请号：US15278576

申请日：2016-09-28

申请人： KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, SEJONG CAMPUS

发明人： Hayun Cecillia Chung

IPC分类号： H04L25/03

CPC分类号： H04L25/03057 ,  H04L25/03878

摘要： Provided is a digital equalizer which outputs a decision value corresponding to reception data transmitted from a data transmitter and is located in a data receiver. The digital equalizer includes at least one flip-flop which stores an adjacent bit sequence which is previous computing information; and a computing device which receives an output value of an analog to digital converter as a first input value, receives the adjacent bit sequence as a second input value, and outputs the decision value which is a binary value of the first input value by referring to a lookup table with respect to the first input value and the second input value.

公开(公告)号：US10411722B2

公开(公告)日：2019-09-10

申请号：US16168336

申请日：2018-10-23

申请人： Korea University Research and Business Foundation, Sejong Campus

发明人： Hayun Cecillia Chung

IPC分类号： H03M1/12 ,  H03M1/16 ,  H03M1/46

摘要： Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.