公开(公告)号：US11104116B2

公开(公告)日：2021-08-31

申请号：US16793535

申请日：2020-02-18

Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

Inventor： Donghwan Kim ,  Se Jin Park ,  Hae-Seok Lee ,  Yoon Mook Kang ,  Hyomin Park ,  Soohyun Bae ,  Jong Won Ko

IPC: B32B43/00 ,  B32B7/12 ,  B32B9/00 ,  B32B17/06 ,  H01L31/048

Abstract: According to one embodiment of the present invention, a method for dismantling a solar cell module for recycling comprises the steps of: providing a silicon solar cell module in which a silicon solar cell element and one side of glass are bonded together by a sealing agent and a transparent conductive material layer is coated between the side of the glass and the sealing agent; applying a high voltage between the transparent conductive material layer and the other side of the glass; and separating the glass and sealing agent by exposing the silicon solar cell module having the transparent conductive material layer discolored by application of the high voltage to a moisture environment.

公开(公告)号：US09467161B1

公开(公告)日：2016-10-11

申请号：US15007368

申请日：2016-01-27

Applicant: Korea University Research and Business Foundation

Inventor： Chul Woo Kim ,  Se Jin Park

IPC: H03M1/38 ,  H03M1/46

CPC classification number: H03M1/145 ,  H03M1/468

Abstract: Provided is a low-power, high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The low-power, high-speed SAR ADC includes a bootstrapping unit configured to receive inputs of first and second analog signals, a double-bit output SAR analog-to-digital conversion unit configured to output a two-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit, and a single-bit output SAR analog-to-digital conversion unit configured to output a one-bit digital signal for each clock cycle section with respect to the first and second analog signals applied through the bootstrapping unit.

Abstract translation: 提供了一种低功耗，高速逐次逼近寄存器（SAR）模数转换器（ADC）。 低功率，高速SAR ADC包括被配置为接收第一和第二模拟信号的输入的自举单元，配置成输出每个时钟的两位数字信号的双位输出SAR模数转换单元 循环部分相对于通过自举单元施加的第一和第二模拟信号，以及单位输出SAR模数转换单元，被配置为针对每个时钟周期部分的第一和第二模拟信号输出一位数字信号 以及通过自举单元施加的第二模拟信号。