公开(公告)号：US20120119305A1

公开(公告)日：2012-05-17

申请号：US12948068

申请日：2010-11-17

申请人： KUO-CHIANG CHEN ,  YEN-YI CHEN ,  CHIEN PING CHOU

发明人： KUO-CHIANG CHEN ,  YEN-YI CHEN ,  CHIEN PING CHOU

IPC分类号： H01L29/78

CPC分类号： H01L29/4238

摘要： A layout of a power MOSFET includes a first zigzag gate structure located on a substrate of the power MOSFET and having a first side and a second side, a first contact located on the substrate and at the first side of the first zigzag gate structure, and a second contact structure located on the substrate and at the second side of the first zigzag gate structure.

摘要翻译： 功率MOSFET的布局包括位于功率MOSFET的衬底上并具有第一侧和第二侧的第一Z字形栅极结构，位于衬底上的第一接触件和位于第一曲折栅极结构的第一侧的第一接触，以及 第二接触结构，其位于所述基板上并位于所述第一曲折栅极结构的第二侧。

公开(公告)号：US20130075882A1

公开(公告)日：2013-03-28

申请号：US13244410

申请日：2011-09-24

申请人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

发明人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

IPC分类号： H01L23/495

CPC分类号： H01L23/49503 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A package structure including a first leadframe, a second leadframe, a power pin, a ground pin, a first pin, several first wires, several second wires, and a package body is disclosed. The first leadframe is used for electrically coupling to the drains of a first power transistor and the second power transistor. The ground pin is electrically coupled to the first leadframe. The first pin is connected with the first leadframe through a conductive region used for increasing the amount of current which can be loaded by the first pin. The first wires are used for electrically coupling between the first leadframe and the source of the second power transistor, for reducing the internal resistance of the second power transistor. The second wires are used for electrically coupling between the ground pin and the source of the first power transistor, for reducing the internal resistance of the first power transistor.

摘要翻译： 公开了一种包括第一引线框，第二引线框，电源引脚，接地引脚，第一引脚，多个第一布线，多个第二布线和封装体的封装结构。 第一引线框架用于电耦合到第一功率晶体管和第二功率晶体管的漏极。 接地引脚电耦合到第一引线框架。 第一引脚通过用于增加可由第一引脚加载的电流量的导电区域与第一引线框架连接。 第一导线用于第一引线框和第二功率晶体管的源之间的电耦合，用于降低第二功率晶体管的内部电阻。 第二导线用于电连接接地引脚与第一功率晶体管的源极之间，用于降低第一功率晶体管的内部电阻。

公开(公告)号：US20120182032A1

公开(公告)日：2012-07-19

申请号：US13008143

申请日：2011-01-18

申请人： KUO-CHIANG CHEN ,  YEN-YI CHEN

发明人： KUO-CHIANG CHEN ,  YEN-YI CHEN

IPC分类号： G01R31/3187

CPC分类号： G01R31/31724

摘要： A test mode controller comprises an enable signal generator, a control signal generator, and a latch. The enable signal generator receives a power signal and a second control signal, and generates a first enable signal and a second enable signal respectively to the latch and the control signal generator. The control signal generator receives a power indicating voltage and a reference voltage, and generates the first control signal to the latch when the first enable signal is enabled. The latch receives the first control signal, and generates the second control signal according to the first control signal when the second enable signal is enabled. The second control signal controls a chip to operate in a test mode or a normal mode. Accordingly, the test mode controller may reduce the test time without a test pin, and may also reduce the chip area and the package cost.

摘要翻译： 测试模式控制器包括使能信号发生器，控制信号发生器和锁存器。 使能信号发生器接收功率信号和第二控制信号，分别产生第一使能信号和第二使能信号给锁存器和控制信号发生器。 控制信号发生器接收功率指示电压和参考电压，并且当第一使能信号被使能时，产生到锁存器的第一控制信号。 锁存器接收第一控制信号，并且当第二使能信号被使能时，根据第一控制信号产生第二控制信号。 第二控制信号控制芯片在测试模式或正常模式下操作。 因此，测试模式控制器可以在没有测试引脚的情况下减少测试时间，并且还可以减少芯片面积和封装成本。

公开(公告)号：US20120139569A1

公开(公告)日：2012-06-07

申请号：US12959641

申请日：2010-12-03

申请人： KUO-CHIANG CHEN ,  YEN-YI CHEN

发明人： KUO-CHIANG CHEN ,  YEN-YI CHEN

IPC分类号： G01R31/3187

CPC分类号： G01R31/31701

摘要： A circuit apparatus includes an input end, an output end, an enable module, a first function module and a second function module. The enable module couples to the input end for receiving an input voltage and outputs an enable signal while the input voltage falls within a first voltage scope. The first function module couples to the enable module and the output end, and performs a test mode according to the enable signal so as to output a test result to the output end. The second function module couples to the input end for receiving the input voltage via the input end and performs a standard mode while the input voltage falls within a second voltage scope.

摘要翻译： 电路装置包括输入端，输出端，使能模块，第一功能模块和第二功能模块。 使能模块耦合到输入端，用于接收输入电压，并在输入电压落在第一电压范围内时输出使能信号。 第一功能模块耦合到使能模块和输出端，并根据使能信号执行测试模式，以便将测试结果输出到输出端。 第二功能模块耦合到输入端，用于经由输入端接收输入电压，并且在输入电压落入第二电压范围内时执行标准模式。

公开(公告)号：US20130075880A1

公开(公告)日：2013-03-28

申请号：US13244344

申请日：2011-09-24

申请人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

发明人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

IPC分类号： H01L23/495

CPC分类号： H01L23/49517 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00014

摘要： A packaging structure comprises a first leadframe, a second leadframe, two grounding pins, two first pins, a plurality of first wires, a plurality of second wires, and a package body. The second leadframe is coupled to the drains of a first power transistor and a second power transistor. The two grounding pins are adjacent together and coupled to the first leadframe. The two first pins are coupled to the source of the second power transistor. The two first pins are connected together through a conductive region for increasing capability of loading current. The plurality of first wires is coupled between the source of the second power transistor and the first pin to decrease the internal resistance of the second power transistor. The plurality of second wires is coupled between the first leadframe and the source of the first power transistor to decrease the internal resistance of the first power transistor.

摘要翻译： 包装结构包括第一引线框架，第二引线框架，两个接地引脚，两个第一引脚，多个第一布线，多个第二布线和封装主体。 第二引线框架耦合到第一功率晶体管和第二功率晶体管的漏极。 两个接地引脚相邻在一起并耦合到第一引线框。 两个第一引脚耦合到第二功率晶体管的源极。 两个第一引脚通过导电区域连接在一起，以增加负载电流的能力。 多个第一布线耦合在第二功率晶体管的源极和第一引脚之间，以降低第二功率晶体管的内部电阻。 多个第二布线耦合在第一引线框架和第一功率晶体管的源极之间，以降低第一功率晶体管的内部电阻。

公开(公告)号：US20120206194A1

公开(公告)日：2012-08-16

申请号：US13028330

申请日：2011-02-16

申请人： KUO-CHIANG CHEN ,  YEN-YI CHEN

发明人： KUO-CHIANG CHEN ,  YEN-YI CHEN

IPC分类号： G05F1/10

CPC分类号： H02J7/0034

摘要： A polarity switch circuit for a charger is disclosed. The circuit includes a polarity switch unit and an input control unit. The polarity switch unit includes an input end, an output end, a correct-direction connecting circuit, and a reverse-direction connecting circuit. The correct-direction connecting circuit has a first switch unit and a second switch unit. When the load is plugged correctly, the positive input node is connected to the positive output node by the first switch unit, and the negative input node is connected to the negative output node by the second switch unit. The reverse-direction connecting circuit includes a third switch unit and a fourth switch unit. When the load is plugged reversely, the positive input node is connected to the negative output node by the third switch unit, and the negative input node is connected to the positive output node by the fourth switch unit.

摘要翻译： 公开了一种用于充电器的极性开关电路。 电路包括极性开关单元和输入控制单元。 极性开关单元包括输入端，输出端，正向连接电路和反向连接电路。 正确方向连接电路具有第一开关单元和第二开关单元。 当负载正确插入时，正输入节点由第一开关单元连接到正输出节点，负输入节点由第二开关单元连接到负输出节点。 反向连接电路包括第三开关单元和第四开关单元。 当负载反向插入时，正输入节点由第三开关单元连接到负输出节点，负输入节点由第四开关单元连接到正输出节点。

公开(公告)号：US20120127671A1

公开(公告)日：2012-05-24

申请号：US12951381

申请日：2010-11-22

申请人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

发明人： KUO-CHIANG CHEN ,  ARTHUR SHAOYAN RONG ,  CHEN HSING LIU ,  YEN-YI CHEN

IPC分类号： H05K7/00

CPC分类号： H01L23/49562 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01M10/425 ,  H01M10/44 ,  H01M10/48 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip module is disclosed to include a pin frame, an electric power switch chip, and a battery protection chip. The pin frame has a chip placement region and six pins. The second pin and the fifth pin are electrically connected at the chip placement region, and the other pins are set electrically isolated from each other. A bottom surface of the electric power switch chip is electrically connected at the chip placement region, and a top surface thereof is electrically connected to the first pin and the third pin. A bottom surface of the battery protection chip is disposed at the top surface of the electric power switch chip in an electrically isolated fashion. A top surface of the battery protection chip is electrically connected to the top surface of the electric power switch chip, the first pin, the fourth pin, and the sixth pin.

摘要翻译： 公开了一种多芯片模块，其包括引脚框架，电力开关芯片和电池保护芯片。 引脚框架有一个芯片放置区域和六个引脚。 第二引脚和第五引脚在芯片布置区域处电连接，并且另一个引脚被设置为彼此电隔离。 电源开关芯片的底表面在芯片布置区域处电连接，并且其顶表面电连接到第一引脚和第三引脚。 电池保护芯片的底表面以电隔离的方式设置在电力开关芯片的顶表面。 电池保护芯片的顶表面电连接到电力开关芯片的顶表面，第一引脚，第四引脚和第六引脚。