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公开(公告)号:US11984268B2
公开(公告)日:2024-05-14
申请号:US17979020
申请日:2022-11-02
Applicant: KYOCERA AVX Components Corporation
Inventor: Marianne Berolini , Jeffrey A. Horn , Richard C. VanAlstine
CPC classification number: H01G4/232 , G01R31/016 , H01G2/065 , H01G4/012 , H01G4/1218 , H01G4/30
Abstract: The present invention is directed to a multilayer ceramic capacitor that includes a plurality of active electrodes and at least one shield electrode that are each arranged within a monolithic body and parallel with a longitudinal direction. The capacitor may exhibit a first insertion loss value at a test frequency, which may be greater than about 2 GHz, in a first orientation relative to the mounting surface. The capacitor may exhibit a second insertion loss value at about the test frequency in a second orientation relative to the mounting surface and the capacitor is rotated 90 degrees or more about the longitudinal direction with respect to the first orientation. The longitudinal direction of the capacitor may be parallel with the mounting surface in each of the first and second orientations. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB.
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公开(公告)号:US11984262B2
公开(公告)日:2024-05-14
申请号:US17680746
申请日:2022-02-25
Applicant: KYOCERA AVX Components Corporation
Inventor: Marianne Berolini , Jeffrey A. Horn , Richard C. VanAlstine
Abstract: A multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers and a plurality of electrode regions. The plurality of electrode regions can include a dielectric region, an active electrode region, and a shield electrode region. The active electrode region may be located between the dielectric region and the shield electrode region in a Z-direction. The dielectric region may extend from the active electrode region to the top surface of the broadband multilayer ceramic capacitor. The capacitor may include a plurality of active electrodes arranged within the active electrode region and at least one shield electrode arranged within the shield electrode region. The dielectric region may be free of electrode layers that extend greater than 25% of a length of the capacitor. A ratio of a capacitor thickness to a thickness of the dielectric region may be less than about 20.
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公开(公告)号:US20220093332A1
公开(公告)日:2022-03-24
申请号:US17541337
申请日:2021-12-03
Applicant: KYOCERA AVX Components Corporation
Inventor: Marianne Berolini , Jeffrey A. Horn , Richard C. VanAlstine
Abstract: A broadband multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers stacked in the Z-direction, a first external terminal, and a second external terminal. A plurality of active electrodes, a bottom shield electrode, and a top shield electrode may be arranged within the monolithic body. The top shield electrode may be positioned between the active electrodes and a top surface of the capacitor and spaced apart from the top surface of the capacitor by a top-shield-to-top distance. A bottom shield electrode may be positioned between the active electrodes and the bottom surface of the capacitor and spaced apart from the bottom surface of the capacitor by a bottom-shield-to-bottom distance. A ratio of the top-shield-to-top distance to the bottom-shield-to-bottom distance may be between about 0.8 and about 1.2. The bottom-shield-to-bottom distance may range from about 8 microns to about 100 microns.
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公开(公告)号:US20230068137A1
公开(公告)日:2023-03-02
申请号:US17979020
申请日:2022-11-02
Applicant: KYOCERA AVX Components Corporation
Inventor: Marianne Berolini , Jeffrey A. Horn , Richard C. VanAlstine
Abstract: The present invention is directed to a multilayer ceramic capacitor that includes a plurality of active electrodes and at least one shield electrode that are each arranged within a monolithic body and parallel with a longitudinal direction. The capacitor may exhibit a first insertion loss value at a test frequency, which may be greater than about 2 GHz, in a first orientation relative to the mounting surface. The capacitor may exhibit a second insertion loss value at about the test frequency in a second orientation relative to the mounting surface and the capacitor is rotated 90 degrees or more about the longitudinal direction with respect to the first orientation. The longitudinal direction of the capacitor may be parallel with the mounting surface in each of the first and second orientations. The second insertion loss value may differ from the first insertion loss value by at least about 0.3 dB.
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公开(公告)号:US20220293348A1
公开(公告)日:2022-09-15
申请号:US17830460
申请日:2022-06-02
Applicant: KYOCERA AVX Components Corporation
Inventor: Marianne Berolini , Jeffrey A. Horn , Richard C. VanAlstine
Abstract: A multilayer capacitor may include a monolithic body including a plurality of dielectric layers. A first external terminal may be disposed along a first end, and a second external terminal may be disposed along a second end of the capacitor. The external terminals may include respective bottom portions that extend along a bottom surface of the capacitor. The bottom portions of the external terminals may be spaced apart by a bottom external terminal spacing distance. A bottom shield electrode may be arranged within the monolithic body between a plurality of active electrodes and the bottom surface of the capacitor. The bottom shield electrode may be spaced apart from the bottom surface of the capacitor by a bottom-shield-to-bottom distance that may range from about 3 microns to about 100 microns. A ratio of a length of the capacitor to the bottom external terminal spacing distance may be less than about 4.
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公开(公告)号:US11664169B2
公开(公告)日:2023-05-30
申请号:US17830460
申请日:2022-06-02
Applicant: KYOCERA AVX Components Corporation
Inventor: Marianne Berolini , Jeffrey A. Horn , Richard C. VanAlstine
CPC classification number: H01G4/302 , H01G2/065 , H01G4/012 , H01G4/1227 , H01G4/2325
Abstract: A multilayer capacitor may include a monolithic body including a plurality of dielectric layers. A first external terminal may be disposed along a first end, and a second external terminal may be disposed along a second end of the capacitor. The external terminals may include respective bottom portions that extend along a bottom surface of the capacitor. The bottom portions of the external terminals may be spaced apart by a bottom external terminal spacing distance. A bottom shield electrode may be arranged within the monolithic body between a plurality of active electrodes and the bottom surface of the capacitor. The bottom shield electrode may be spaced apart from the bottom surface of the capacitor by a bottom-shield-to-bottom distance that may range from about 3 microns to about 100 microns. A ratio of a length of the capacitor to the bottom external terminal spacing distance may be less than about 4.
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公开(公告)号:US20220189691A1
公开(公告)日:2022-06-16
申请号:US17680746
申请日:2022-02-25
Applicant: KYOCERA AVX Components Corporation
Inventor: Marianne Berolini , Jeffrey A. Horn , Richard C. VanAlstine
Abstract: A multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers and a plurality of electrode regions. The plurality of electrode regions can include a dielectric region, an active electrode region, and a shield electrode region. The active electrode region may be located between the dielectric region and the shield electrode region in a Z-direction. The dielectric region may extend from the active electrode region to the top surface of the broadband multilayer ceramic capacitor. The capacitor may include a plurality of active electrodes arranged within the active electrode region and at least one shield electrode arranged within the shield electrode region. The dielectric region may be free of electrode layers that extend greater than 25% of a length of the capacitor. A ratio of a capacitor thickness to a thickness of the dielectric region may be less than about 20.
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公开(公告)号:US11728092B2
公开(公告)日:2023-08-15
申请号:US17541337
申请日:2021-12-03
Applicant: KYOCERA AVX Components Corporation
Inventor: Marianne Berolini , Jeffrey A. Horn , Richard C. VanAlstine
CPC classification number: H01G4/012 , H01G4/1227 , H01G4/2325 , H01G4/30
Abstract: A broadband multilayer ceramic capacitor may include a monolithic body including a plurality of dielectric layers stacked in the Z-direction, a first external terminal, and a second external terminal. A plurality of active electrodes, a bottom shield electrode, and a top shield electrode may be arranged within the monolithic body. The top shield electrode may be positioned between the active electrodes and a top surface of the capacitor and spaced apart from the top surface of the capacitor by a top-shield-to-top distance. A bottom shield electrode may be positioned between the active electrodes and the bottom surface of the capacitor and spaced apart from the bottom surface of the capacitor by a bottom-shield-to-bottom distance. A ratio of the top-shield-to-top distance to the bottom-shield-to-bottom distance may be between about 0.8 and about 1.2. The bottom-shield-to-bottom distance may range from about 8 microns to about 100 microns.
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