摘要:
Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.
摘要:
A method and apparatus for automatic configuration of multiple on-chip interconnects have been described. In one embodiment, the invention reduces the configuration time of several on-chip network features, and also ensures that these features are configured correctly to minimize errors in a design.
摘要:
Methods and apparatuses for optimizing distributed multiplexed bus interconnects are described. Parameters of components that make up a distributed multiplexed bus interconnect may be optimized, such as an amount of area on a chip occupied by the component, an amount of power consumed by the component, etc., while satisfying existing timing constraints between nodes of a distributed multiplexed bus interconnect.
摘要:
Methods and apparatuses are described for incorporating floor planning information into a configuration process by generating a definition of a floor plan grouping of interconnect components during a front-end view design process for the interconnect. Further, a user is permitted to combine components from separate IP block representations of interconnects during the front-end view design process, based upon physical location of the grouping of the components making up the interconnects on the chip.
摘要:
A method and apparatus for optimizing distributed multiplexed bus interconnects are described. The multiplexed bus interconnect contains one or more multiplexers to route signals through the bus interconnect. An amount of signaling wiring present within a distributed multiplexed bus interconnect is optimized by eliminating individual signaling wires based upon whether an Intellectual Property core connected to the multiplexed bus interconnect transmits or receives signals from the distributed multiplexed bus interconnect.