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    INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR
    1.
    发明申请
    INTEGRATED CIRCUIT WITH A THIN BODY FIELD EFFECT TRANSISTOR AND CAPACITOR 失效
    具有薄体场效应晶体管和电容器的集成电路

    公开(公告)号：US20130178021A1

    公开(公告)日：2013-07-11

    申请号：US13614908

    申请日：2012-09-13

    申请人： Kangguo CHENG ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Ghavam G. SHAHIDI

    发明人： Kangguo CHENG ,  Bruce DORIS ,  Ali KHAKIFIROOZ ,  Ghavam G. SHAHIDI

    IPC分类号： H01L21/84

    CPC分类号： H01L21/84 ,  H01L21/32053 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/41783

    摘要： A transistor region of a first semiconductor layer and a capacitor region in the first semiconductor layer are isolated. A dummy gate structure is formed on the first semiconductor layer in the transistor region. A second semiconductor layer is formed on the first semiconductor layer. First and second portions of the second semiconductor layer are located in the transistor region, and a third portion of the second semiconductor layer is located in the capacitor region. First, second, and third silicide regions are formed on the first, second, and third portions of the second semiconductor layer, respectively. After forming a dielectric layer, the dummy gate structure is removed forming a first cavity. At least a portion of the dielectric layer located above the third silicide region is removed forming a second cavity. A gate dielectric is formed in the first cavity and a capacitor dielectric in the second cavity.

    摘要翻译： 隔离第一半导体层中的第一半导体层和电容器区域的晶体管区域。 在晶体管区域的第一半导体层上形成虚拟栅极结构。 在第一半导体层上形成第二半导体层。 第二半导体层的第一和第二部分位于晶体管区域中，第二半导体层的第三部分位于电容器区域中。 第一，第二和第三硅化物区分别形成在第二半导体层的第一，第二和第三部分上。 在形成电介质层之后，去除伪栅极结构形成第一腔。 位于第三硅化物区域上方的电介质层的至少一部分被去除，形成第二腔。 在第一腔中形成栅极电介质，在第二腔中形成电容器电介质。

    FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION
    2.
    发明申请
    FORMATION OF EMBEDDED STRESSOR THROUGH ION IMPLANTATION 有权
    通过离子植入形成嵌入式压力器

    公开(公告)号：US20120313168A1

    公开(公告)日：2012-12-13

    申请号：US13155878

    申请日：2011-06-08

    申请人： Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Ghavam G. SHAHIDI

    发明人： Kangguo CHENG ,  Bruce B. DORIS ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Ghavam G. SHAHIDI

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/78654

    摘要： An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.

    摘要翻译： 极薄的绝缘体上硅晶体管包括在衬底上方的掩埋氧化物层。 掩埋氧化物层例如具有小于50nm的厚度。 硅层在掩埋氧化物层之上。 硅层上的栅极叠层包括至少形成在硅层上的栅极电介质和形成在栅极电介质上的栅极导体。 栅极间隔物在硅层上具有第一部分，第二部分邻近栅极堆叠。 第一升高的源极/漏极区域和第二升高的源极/漏极区域各自具有包括硅层的一部分的第一部分和与栅极间隔物相邻的第二部分。 至少部分地在衬底内形成至少一个嵌入式应力器，其在硅层中形成的硅沟道区域上施加预定的应力。

    SOI Trench Dram Structure With Backside Strap
    3.
    发明申请
    SOI Trench Dram Structure With Backside Strap 审中-公开

    公开(公告)号：US20120302020A1

    公开(公告)日：2012-11-29

    申请号：US13568580

    申请日：2012-08-07

    申请人： Bruce B. DORIS ,  Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Ghavam G. SHAHIDI

    发明人： Bruce B. DORIS ,  Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Pranita KULKARNI ,  Ghavam G. SHAHIDI

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

    摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.