Method to form low series resistance transistor devices on silicon on insulator layer
    1.
    发明授权
    Method to form low series resistance transistor devices on silicon on insulator layer 有权
    在绝缘体硅层上形成低串联电阻晶体管器件的方法

    公开(公告)号:US08440552B1

    公开(公告)日:2013-05-14

    申请号:US13346008

    申请日:2012-01-09

    IPC分类号: H01L21/225

    摘要: A method includes providing an ETSOI wafer having a semiconductor layer having a top surface with at least one gate structure having on sidewalls thereof a layer of dielectric material. A portion of the layer of dielectric material extends away from the gate structure on the surface of the semiconductor layer. The method further includes faulting a raised S/D on the semiconductor layer adjacent to the portion of the layer of dielectric material, removing the portion of the layer of dielectric material to expose an underlying portion of the surface of the semiconductor layer and applying a layer of glass containing a dopant to cover at least the exposed portion of the surface of the semiconductor layer. The method further includes diffusing the dopant through the exposed portion of the surface of the semiconductor layer to form a source extension region and a drain extension region.

    摘要翻译: 一种方法包括提供具有半导体层的ETSOI晶片,所述半导体层具有顶表面,所述半导体层具有至少一个在其侧壁上具有介电材料层的栅极结构。 电介质材料层的一部分远离半导体层表面上的栅极结构延伸。 该方法还包括将邻近该介电材料层的部分的半导体层上的升高的S / D断开,去除介电材料层的该部分以暴露该半导体层表面的下面部分并施加一层 的含有掺杂剂的玻璃以至少覆盖半导体层的表面的暴露部分。 该方法还包括通过半导体层的表面的暴露部分扩散掺杂剂以形成源极延伸区域和漏极延伸区域。