利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

277 条记录 (耗时 0.034 秒)

    Non-relaxed embedded stressors with solid source extension regions in CMOS devices
    1.
    发明授权
    Non-relaxed embedded stressors with solid source extension regions in CMOS devices 失效
    CMOS器件中具有固态源延伸区域的非轻松嵌入式应力源

    公开(公告)号：US08592270B2

    公开(公告)日：2013-11-26

    申请号：US13115314

    申请日：2011-05-25

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Douglas C. La Tulipe, Jr.

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Douglas C. La Tulipe, Jr.

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/823807

    摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.

    摘要翻译： 形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

    NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES
    2.
    发明申请
    NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES 失效
    CMOS器件中固体源扩展区非松弛嵌入式压电器

    公开(公告)号：US20120302019A1

    公开(公告)日：2012-11-29

    申请号：US13115314

    申请日：2011-05-25

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Douglas C. La Tulipe, JR.

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Douglas C. La Tulipe, JR.

    IPC分类号： H01L21/8238 ,  H01L21/336

    CPC分类号： H01L21/823814 ,  H01L21/823807

    摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.

    摘要翻译： 形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

    Junctionless transistor
    6.
    发明授权
    Junctionless transistor 有权
    无结晶体晶体管

    公开(公告)号：US08803233B2

    公开(公告)日：2014-08-12

    申请号：US13242861

    申请日：2011-09-23

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

    IPC分类号： H01L29/778

    CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78654 ,  H01L29/78696

    摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.

    摘要翻译： 晶体管包括半导体层，并且在半导体层上形成栅极电介质。 栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。 有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。 该渐变掺杂剂区域的掺杂浓度逐渐降低。 晶体管还包括与有源区相邻的源区和漏区。 源极和漏极区域和有源区域具有相同的导电类型。

    Inversion mode varactor
    7.
    发明授权
    Inversion mode varactor 有权
    反转模式变容二极管

    公开(公告)号：US08564040B1

    公开(公告)日：2013-10-22

    申请号：US13570360

    申请日：2012-08-09

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

    IPC分类号： H01L27/108

    CPC分类号： H01L29/93 ,  H01L27/1203 ,  H01L29/66174

    摘要： In one exemplary embodiment of the invention, a method includes: providing an inversion mode varactor having a substrate, a backgate layer overlying the substrate, an insulating layer overlying the backgate layer, a semiconductor layer overlying the insulating layer and at least one metal-oxide semiconductor field effect transistor (MOSFET) device disposed upon the semiconductor layer, where the semiconductor layer includes a source region and a drain region, where the at least one MOSFET device includes a gate stack defining a channel between the source region and the drain region, where the gate stack has a gate dielectric layer overlying the semiconductor layer and a conductive layer overlying the gate dielectric layer; and applying a bias voltage to the backgate layer to form an inversion region in the semiconductor layer at an interface between the semiconductor layer and the insulating layer.

    摘要翻译： 在本发明的一个示例性实施例中，一种方法包括：提供具有衬底的倒置模式变容二极管，覆盖衬底的背栅层，覆盖在背栅层上的绝缘层，覆盖绝缘层的半导体层和至少一种金属氧化物 半导体场效应晶体管（MOSFET）器件，其设置在所述半导体层上，其中所述半导体层包括源极区和漏极区，其中所述至少一个MOSFET器件包括限定所述源极区和所述漏极区之间的沟道的栅极叠层， 其中所述栅极堆叠具有覆盖所述半导体层的栅极介电层和覆盖所述栅极介电层的导电层; 以及向所述背栅层施加偏置电压，以在所述半导体层和所述绝缘层之间的界面处在所述半导体层中形成反转区域。

    SOI trench DRAM structure with backside strap
    9.
    发明授权
    SOI trench DRAM structure with backside strap 有权
    具有背面带的SOI沟槽DRAM结构

    公开(公告)号：US08318574B2

    公开(公告)日：2012-11-27

    申请号：US12847208

    申请日：2010-07-30

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L21/20

    CPC分类号： H01L27/1203 ,  H01L27/10829 ,  H01L27/10867

    摘要： In one exemplary embodiment, a semiconductor structure including: a SOI substrate having of a top silicon layer overlying an insulation layer, the insulation layer overlies a bottom silicon layer; a capacitor disposed at least partially in the insulation layer; a device disposed at least partially on the top silicon layer, where the device is coupled to a doped portion of the top silicon layer; a backside strap of first epitaxially-deposited material, at least a first portion of the backside strap underlies the doped portion of the top silicon layer, the backside strap is coupled to the doped portion of the top silicon layer at a first end of the backside strap and to the capacitor at a second end of the backside strap; and second epitaxially-deposited material that at least partially overlies the doped portion of the top silicon layer, the second epitaxially-deposited material further at least partially overlies the first portion.

    摘要翻译： 在一个示例性实施例中，一种半导体结构，包括：具有覆盖绝缘层的顶部硅层的SOI衬底，所述绝缘层覆盖在底部硅层上; 至少部分地设置在绝缘层中的电容器; 至少部分地设置在所述顶部硅层上的器件，其中所述器件耦合到所述顶部硅层的掺杂部分; 第一外延沉积材料的背面带，背侧带的至少第一部分位于顶部硅层的掺杂部分的下面，背面带在背面的第一端耦合到顶部硅层的掺杂部分 带子和背部带子的第二端处的电容器; 以及至少部分地覆盖在顶部硅层的掺杂部分上的第二外延沉积材料，第二外延沉积材料还至少部分地覆盖在第一部分上。