公开(公告)号：US06219107B1

公开(公告)日：2001-04-17

申请号：US09139038

申请日：1998-08-24

申请人： Karl H. Renner ,  Apparajan Ganesan

发明人： Karl H. Renner ,  Apparajan Ganesan

IPC分类号： H04N552

CPC分类号： H04N5/52

摘要： A video decoder circuit is provided with automatic AGC bias voltage calibration. The video decoder circuit has an input for receiving a video signal that is capacitively coupled to an analog front-end circuit. The decoder circuit includes a microprocessor-based control circuit coupled to the analog front-end circuit. The control circuit includes a bias circuit, a gain interface circuit for changing the amplitude of the video signal prior to filtering in a filter circuit, an offset circuit for changing the DC-level shift of the video signal, and a switching circuit for switching into a calibration mode by bypassing the filter circuit and connecting the gain interface circuit directly to an analog-to-digital conversion circuit of the analog front-end circuit.

摘要翻译： 视频解码器电路具有自动AGC偏置电压校准。 视频解码器电路具有用于接收与模拟前端电路电容耦合的视频信号的输入。 解码器电路包括耦合到模拟前端电路的基于微处理器的控制电路。 控制电路包括偏置电路，用于在滤波电路中滤波之前改变视频信号的幅度的增益接口电路，用于改变视频信号的直流电平偏移的偏移电路，以及切换电路 通过旁路滤波器电路并将增益接口电路直接连接到模拟前端电路的模拟 - 数字转换电路的校准模式。

公开(公告)号：US4740906A

公开(公告)日：1988-04-26

申请号：US646381

申请日：1984-08-31

申请人： Karl H. Renner ,  Alec J. Morton

发明人： Karl H. Renner ,  Alec J. Morton

IPC分类号： G10L19/06 ,  G06F7/544 ,  G06F17/10 ,  G10L11/00 ,  G10L19/04 ,  H03H17/02 ,  G06F15/31 ,  G10L1/00

CPC分类号： H03H17/0285 ,  G06F7/5443

摘要： A lattice filter for processing lattice equations includes a fast adder (78) for adding partial products to partially perform a multiplication step. A full adder (44) is provided for completing the multiplication and then adding the product with a previously calculated and stored value. The input to the full adder (44) is multiplexed with a multiplexer (74) for selecting the sum output of the fast adder (78) and a multiplexer (76) for selecting the carry output of the fast adder (78). The multiplexer (74) also selects prestored values for addition with the summed output of the full adder (44). This summed output is selected by the multiplexer (76). The fast adder (78) sums partial products simultaneous with addition operations of the full adder (44). In this manner, the full adder (44) operates at a slower rate than the fast adder (78). Storage registers (58), (62), (70) are utilized to delay results output by the full adder (44) for later selection and operation thereon. These values are utilized as both the multiplicand the addend in subsequent operations. The multiplier is stored in a K-stack (90) and selected for the appropriate operations. A bit correction circuit (190) provides corrections for truncated bits in the form of a carry input to the full adder (44).

摘要翻译： 用于处理晶格方程的晶格滤波器包括用于部分地执行乘法步骤的部分乘积的快速加法器（78）。 提供一个完整加法器（44）用于完成乘法，然后将乘积与先前计算和存储的值相加。 对全加器（44）的输入与用于选择快速加法器（78）的和输出的复用器（74）和用于选择快速加法器（78）的进位输出的多路复用器（76）复用。 多路复用器（74）还用全加器（44）的相加输出选择用于相加的预存值。 该相加输出由多路复用器（76）选择。 快速加法器（78）将全部加法器（44）的加法运算同时产生部分乘积。 以这种方式，全加器（44）以比快速加法器（78）更慢的速率工作。 存储寄存器（58），（62），（70）用于延迟由全加器（44）输出的结果，用于其后的选择和操作。 这些值被用作后续操作中的被乘数加数。 乘法器存储在K堆栈（90）中，并进行适当的操作。 位校正电路（190）以对进位输入的形式对全加器（44）提供校正。

公开(公告)号：US4695970A

公开(公告)日：1987-09-22

申请号：US646869

申请日：1984-08-31

申请人： Karl H. Renner ,  Alec J. Morton

发明人： Karl H. Renner ,  Alec J. Morton

IPC分类号： G06F17/10 ,  G10L19/06 ,  G10L19/14 ,  H03H17/02 ,  G06F15/31 ,  G10L1/00

CPC分类号： H03H17/0285 ,  G10L19/16 ,  G10L19/06

摘要： An LPC digital lattice filter includes a full adder (44) which has one input thereof multiplexed with a multiplexer (46) and the other input thereof multiplexed by a multiplexer (50). Combination of the multiplication and addition steps with the full adder (44) results in the calculation of one of the digital filter equations. The result of each of these equations is either a Y-value or a B-value. The Y-values are stored in the output of a Y-register (78) and the B-values are stored in a nine stage B-stack (100) for delay thereof. The multiplexer (60) selects multiplicands from either the output of the one stage delay (86), from the B-stack (100) or the input excitation I. The multiplexer (46) selects addends from either the output of the B-stack (100), the output of the B-register (96) or from the multiplexers (60) or (66). The values are calculated in an interleaved sequence with a Y-value calculated and then a B-value calculated utilizing this generated Y-value. This generated Y-value is then used in calculating the next sequential Y-value and then discarded. However, the B-values are delayed until calculation of the next set of equations. The interleaved sequence allows use of only one set of delay stages.

摘要翻译： LPC数字网格滤波器包括全加器（44），其具有与多路复用器（46）复用的一个输入端，而另一输入端由多路复用器（50）复用。 乘法和加法步骤与全加器（44）的组合导致计算一个数字滤波器方程。 这些等式的每一个的结果是Y值或B值。 Y值存储在Y寄存器（78）的输出中，并且B值存储在九级B堆栈（100）中用于延迟。 多路复用器（60）从一级延迟（86）的输出，从B堆栈（100）或输入激励I中选择被乘数。多路复用器（46）从B堆栈的输出中选择加数 （100），B寄存器（96）的输出或多路复用器（60）或（66）的输出。 以计算的Y值的交错序列计算值，然后使用该生成的Y值计算B值。 然后将该生成的Y值用于计算下一个顺序Y值，然后丢弃。 然而，B值延迟到下一组方程的计算。 交错序列允许仅使用一组延迟级。

公开(公告)号：US4796216A

公开(公告)日：1989-01-03

申请号：US86225

申请日：1987-08-13

申请人： Karl H. Renner ,  Alec J. Morton

发明人： Karl H. Renner ,  Alec J. Morton

IPC分类号： G06F7/52 ,  G10L19/04 ,  G10L19/14 ,  H03H17/02 ,  G06F7/38 ,  G10L5/02

CPC分类号： G10L19/16 ,  G06F7/5338 ,  H03H17/0225

摘要： A digital filter for synthesized speech includes a full adder (72) that is multiplexed to perform multiplication and addition/subtraction operations. The inputs of the adder (72) are multiplexed by multiplexers (90) and (92). The adder (72) calculates Y-values and B-values. The B-values are input to a delay stack (116) and the Y-values are stored in a Y-register (78). One product is generated of a multiplier stored in a K-stack (128) and a multiplicand selected by a multiplexer (122). The multiplicand is a prestored summation that was earlier stored in a sum register (82). This product is stored in an ACC register (74) and utilized in both the calculation of the B-values and the Y-values. Therefore, only one multiplication is required for corresponding Y- and B-values, thereby reducing the number of multiplication steps required in processing each stage of a digital filter.

摘要翻译： 用于合成语音的数字滤波器包括多路复用以执行乘法和加法/减法运算的全加器（72）。 加法器（72）的输入由多路复用器（90）和（92）复用。 加法器（72）计算Y值和B值。 B值被输入到延迟堆栈（116），Y值被存储在Y寄存器（78）中。 一个产品由存储在K堆栈（128）中的乘法器和由多路复用器（122）选择的被乘数产生。 被乘数是预先存储在和寄存器（82）中的求和。 该产品存储在ACC寄存器（74）中，并用于计算B值和Y值。 因此，对于相应的Y和B值仅需要一次乘法，从而减少处理数字滤波器的每一级所需的乘法步数。

公开(公告)号：US4686644A

公开(公告)日：1987-08-11

申请号：US646606

申请日：1984-08-31

申请人： Karl H. Renner ,  Alec J. Morton

发明人： Karl H. Renner ,  Alec J. Morton

IPC分类号： G10L19/04 ,  G06F15/31 ,  G10L1/00

CPC分类号： G10L19/04

摘要： A digital lattice filter includes a Y-adder (44) and a B-adder (106). The Y-adder (44) calculates the Y-values for a linear predictive coding voice compression technique and the B-adder (106) calculates the B-values. Each of the calculated B-values output by the B-adder (106) is input to a B-stack (118) for storage therein. The B-stack (118) delays the B-values for one sample period. Multiplier constants are contained in a K-stack (90) for output to both adders (44) and (106) for use in the multiplication operation. The final value is stored in a Y1-register (104). Each of the adders (44) and (106) are multiplexed to perform a multiplication operation followed by an addition operation to generate the respective Y- and B-values. A generated Y-value is stored in a Y-register (56) for use in the next sequential Y calculation. In addition, the generated Y-value is used as a multiplicand for generation of a B-value. Therefore, it is only necessary to store the Y-values for one clock cycle and the B-values for up to nine clock cycles, thus reducing the amount of storage space necessary. In addition, the use of two multiplexed adders reduces the required processing speed at each of the adders.

摘要翻译： 数字格子滤波器包括Y加法器（44）和B加法器（106）。 Y加法器（44）计算线性预测编码语音压缩技术的Y值，B加法器（106）计算B值。 由B加法器（106）输出的每个计算的B值被输入到B堆叠（118）以便存储在其中。 B堆栈（118）延迟一个采样周期的B值。 乘法器常数包含在K堆叠（90）中，用于输出到用于乘法运算的两个加法器（44）和（106）。 最终值存储在Y1寄存器（104）中。 加法器（44）和（106）中的每一个被复用以执行乘法运算，随后加法运算以产生相应的Y和B值。 所生成的Y值被存储在Y寄存器（56）中，用于下次顺序Y计算。 另外，生成的Y值被用作生成B值的被乘数。 因此，只需要存储一个时钟周期的Y值和最多9个时钟周期的B值，从而减少必要的存储空间。 另外，使用两个多路复用加法器减少了每个加法器所需的处理速度。

公开(公告)号：US4700323A

公开(公告)日：1987-10-13

申请号：US646868

申请日：1984-08-31

申请人： Karl H. Renner ,  Alec J. Morton

发明人： Karl H. Renner ,  Alec J. Morton

IPC分类号： G06F7/544 ,  H03H17/02 ,  G06F15/31 ,  G10L1/00

CPC分类号： H03H17/0285 ,  G06F7/5443 ,  H03H17/02

摘要： A system for processing a plurality of Equations includes a single full adder (44) which has the A input thereof multiplexed by multiplexer (62) and the B input thereof multiplexed by a multiplexer (94) and a multiplexer (66). The multiplexer (94) is operable to select a multiplicand for multiplication operations from a delay stack (54) for multiplication operations. The multiplication operation is performed by adding together partial products recording to Booth's modified algorithm. The partial products are generated by recode logic circuit (90) and (98). The recode logic circuits (90) and (98) are controlled by the multiplexed output from the multiplexer (80) which selects bits of a given multiplier stored in a K-stack (72). The multiplexer (62) in conjunction with the recode logic circuits (90) and (98) control reconfiguration of the adder (44) as a multiplication circuit. The addition operation is performed on the generated product by circulating the product back to the B-input of the adder (44) through the multiplexer (66). Data is selected from the output of a data stack (52) or from a D-register (108) which contains a prestored output value.

摘要翻译： 一种用于处理多个等式的系统包括一个单个全加器（44），其具有由多路复用器（62）复用的A输入端，并且由多路复用器（94）和多路复用器（66）复用的B输入端。 复用器（94）可操作以从用于乘法运算的延迟堆栈（54）中选择用于乘法运算的被乘数。 通过将部分产品记录添加到Booth的修改算法中来执行乘法运算。 部分产品由重新编码逻辑电路（90）和（98）产生。 重新编码逻辑电路（90）和（98）由多路复用器（80）的复用输出控制，该复用器选择存储在K堆栈（72）中的给定乘法器的位。 多路复用器（62）结合重新编码逻辑电路（90）和（98）控制加法器（44）的重配置作为乘法电路。 通过多路复用器（66）将产品循环回加法器（44）的B输入端，对产生的乘积进行加法运算。 从数据堆栈（52）的输出或包含预存储的输出值的D寄存器（108）中选择数据。

公开(公告)号：US4114366A

公开(公告)日：1978-09-19

申请号：US710524

申请日：1976-08-02

申请人： Karl H. Renner ,  Clark Russell Williams

发明人： Karl H. Renner ,  Clark Russell Williams

IPC分类号： G04G9/00 ,  G04B19/30 ,  G04C3/00 ,  H05B37/02 ,  H05B39/04

CPC分类号： G04G9/0017

摘要： A digital light-sensing control system for use in light sensitive equipment, such as a digital watch or a camera, is comprised of light sensor means such as a photo resistor, a digital brightness detector, and brightness control logic. The light sensor means produces analog signals which vary with ambient light intensity. The digital brightness detector selectively digitizes the analog signals to generate digital brightness signals. The brightness control logic generates system control signals in response to the digital brightness signals. Several embodiments of the digital brightness detector and the brightness control logic are disclosed. Each embodiment is capable of being integrated on a single semiconductor substrate.

摘要翻译： 用于光敏设备（例如数字手表或照相机）的数字光感测控制系统由诸如光电阻器，数字亮度检测器和亮度控制逻辑的光传感器装置组成。 光传感器装置产生随着环境光强度而变化的模拟信号。 数字亮度检测器选择性地数字化模拟信号以产生数字亮度信号。 亮度控制逻辑响应于数字亮度信号产生系统控制信号。 公开了数字亮度检测器和亮度控制逻辑的几个实施例。 每个实施例能够集成在单个半导体衬底上。

公开(公告)号：US07046306B2

公开(公告)日：2006-05-16

申请号：US10404191

申请日：2003-03-31

申请人： Fan Zhai ,  Karl H. Renner

发明人： Fan Zhai ,  Karl H. Renner

IPC分类号： D06F71/08

CPC分类号： H04N9/78

摘要： In one embodiment, a method for processing a video signal includes: (1) receiving and storing luminance and chrominance information for each pixel in a first portion of the signal; (2) receiving luminance and chrominance information for each pixel in a second portion of the signal; (3) determining an estimated motion vector for each particular pixel of the second portion by comparing the luminance and chrominance information of the particular pixel to the stored luminance and chrominance information for one or more pixels in a search area of the first portion to determine a pixel in the search area that most closely matches the particular pixel and determining the estimated motion vector according to the particular pixel and the most closely matching pixel; (4) using the estimated motion vector to access the chrominance information for the most closely matching pixel; (5) using a three-dimensional comb filter to filter the chrominance information for the particular pixel and for the most closely matching pixel to determine three-dimensional filter output chrominance information for the particular pixel; (6) receiving the three-dimensional output chrominance information and if the chrominance information for the particular pixel matches the chrominance information of the most closely matching pixel within a specified tolerance, using the three-dimensional filter output chrominance information to determine output luminance information for the particular pixel; and (7) providing the three-dimensional output chrominance information and output luminance information for the particular pixel for displaying the particular pixel.

摘要翻译： 在一个实施例中，一种用于处理视频信号的方法包括：（1）在信号的第一部分中接收和存储每个像素的亮度和色度信息; （2）在信号的第二部分中接收每个像素的亮度和色度信息; （3）通过将特定像素的亮度和色度信息与存储在第一部分的搜索区域中的一个或多个像素的亮度和色度信息相比较来确定第二部分的每个特定像素的估计运动矢量，以确定 搜索区域中与所述特定像素最匹配的像素，并且根据所述特定像素和最匹配的像素确定所述估计的运动矢量; （4）使用估计的运动矢量来访问最匹配的像素的色度信息; （5）使用三维梳状滤波器对特定像素和最匹配的像素的色度信息进行滤波，以确定特定像素的三维滤波器输出色度信息; （6）接收三维输出色度信息，并且如果特定像素的色度信息与指定容差内的最匹配像素的色度信息匹配，则使用三维滤波器输出色度信息来确定输出亮度信息， 特定像素 和（7）提供用于显示特定像素的特定像素的三维输出色度信息和输出亮度信息。

公开(公告)号：US06366327B1

公开(公告)日：2002-04-02

申请号：US09126629

申请日：1998-07-30

申请人： Karl H. Renner ,  Weider Peter Chang

发明人： Karl H. Renner ,  Weider Peter Chang

IPC分类号： H04N514

CPC分类号： H04N5/46 ,  H04N5/10

摘要： A technique for detecting three modes of video input signal and outputting a vertical sync signal based on the input signal. In a first mode, a standard video signal is received and a line counter is used to decode and output the vertical sync. In a second mode where a non-standard signal is received, line counter cannot be used, but a vertical sync is detected and output. In a third mode, no video input signal is received, yet a vertical sync is output in free-running mode so that a blank screen is displayed.

摘要翻译： 一种用于检测视频输入信号的三种模式并基于输入信号输出垂直同步信号的技术。 在第一模式中，接收标准视频信号，并且使用行计数器来解码并输出垂直同步。 在接收到非标准信号的第二模式中，不能使用行计数器，而是检测并输出垂直同步信号。 在第三模式中，没有接收到视频输入信号，但是以自由运行模式输出垂直同步，从而显示空白屏幕。