公开(公告)号：US5652853A

公开(公告)日：1997-07-29

申请号：US455818

申请日：1995-05-31

申请人： Karl Jean Duvalsaint ,  Peter Hermon Gum ,  Moon Ju Kim ,  Barry Watson Krumm ,  Donald William McCauley ,  John Fenton Scanlon

发明人： Karl Jean Duvalsaint ,  Peter Hermon Gum ,  Moon Ju Kim ,  Barry Watson Krumm ,  Donald William McCauley ,  John Fenton Scanlon

IPC分类号： G06F9/46 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0284

摘要： A memory reconfiguration system now allows a guest's absolute storage space to be mapped to multiple discontiguous host absolute storage space. A multi-zone relocation facility is provided for relocating multiple zones of the memory of the computer system. A control program being executed in its data processing system to reconfigure storages that are assigned to guests when sufficient real addressing capability is not available to provide a range of holes in the host absolute addressing space. Memory can be reconfigured by a control program that allows main storage, and expanded storage associated with a guest's real storage to be mapped to multiple discontiguous areas of host absolute spaces. When sufficient real addressing is not available in the host absolute addressing space it allows expansion of the host absolute storage space that maps a guest storage. The system can be used in scalar, parallel and massively parallel computer systems having plural logical processors (LPARs).

摘要翻译： 内存重新配置系统现在允许将访客的绝对存储空间映射到多个不连续的主机绝对存储空间。 提供了多区域搬迁设施，用于重新定位计算机系统的存储器的多个区域。 在其数据处理系统中正在执行的控制程序，以在足够的实际寻址能力不可用于在主机绝对寻址空间中提供一系列空穴时重新配置分配给客人的存储。 存储器可以由允许主存储的控制程序重新配置，并且与客人的真实存储相关联的扩展存储被映射到主机绝对空间的多个不连续的区域。 当主机绝对寻址空间中没有足够的实际寻址时，它可以扩展映射guest虚拟机存储的主机绝对存储空间。 该系统可用于具有多个逻辑处理器（LPAR）的标量，并行和大规模并行计算机系统。

公开(公告)号：US5684975A

公开(公告)日：1997-11-04

申请号：US453140

申请日：1995-05-30

申请人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

发明人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F12/02

CPC分类号： G06F12/109 ,  G06F12/10

摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

摘要翻译： 在处理系统中，在虚拟地址和绝对地址之间便于翻译。 该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。 加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。 逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。 该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。 从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

公开(公告)号：US5649140A

公开(公告)日：1997-07-15

申请号：US414671

申请日：1995-03-31

申请人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

发明人： Karl Jean Duvalsaint ,  Mark Steven Farrell ,  Barry Watson Krumm ,  Donald William McCauley ,  Charles Franklin Webb

IPC分类号： G06F12/10 ,  G06F9/26 ,  G06F9/34 ,  G06F12/00 ,  G06F12/02

CPC分类号： G06F12/109 ,  G06F12/10

摘要： In a processing system, a translation is facilitated between a virtual address and an absolute address. The system includes multiple registers and a mechanism for loading them with a first set of address translation parameters. An adder sums a translation origin register with an offset register to produce a base-plus-offset value. A logic circuit selectively combines selected registers and the base-plus-offset value to produce an address of a translation table entry which facilitates a determination of the absolute address. This determination includes performing one or more of prefixing, windowing, zoning and memory begin. A latency of the system from a presentation of the translation origin register to the adder to the output of the translation table entry from the logic circuit is at most one clock cycle.

摘要翻译： 在处理系统中，在虚拟地址和绝对地址之间便于翻译。 该系统包括多个寄存器和用第一组地址转换参数加载它们的机制。 加法器将平移原点寄存器与偏移寄存器相加以产生基准加偏移值。 逻辑电路选择性地组合所选择的寄存器和基本加偏移值以产生有助于确定绝对地址的转换表条目的地址。 该确定包括执行前缀，加窗，分区和存储器开始中的一个或多个。 从转换起始寄存器到加法器的表示到逻辑电路的转换表项的输出的系统的等待时间最多为一个时钟周期。

公开(公告)号：US6122638A

公开(公告)日：2000-09-19

申请号：US979597

申请日：1997-11-26

申请人： Gary Douglas Huber ,  Donald William McCauley

发明人： Gary Douglas Huber ,  Donald William McCauley

IPC分类号： G06F9/318 ,  G06F17/30

CPC分类号： G06F9/30174 ,  G06F9/3879 ,  Y10S707/99944 ,  Y10S707/99945

摘要： An object-oriented processor and method of operating such a processor are disclosed. According to the method, in response to receiving a first instruction that references a first object having both data and at least a first method associated therewith, an address of the first method is calculated. In addition, at least one pointer is cached that indicates (possibly together with other pointers) the address of the first method. In response to receipt of a subsequent second instruction that references a second object having both data and one or more methods associated therewith, where the one or more methods include the first method, the address of a second method associated with the second object is determined by reference to the cached pointer. In a preferred embodiment of the present invention, the first and second methods comprise the same method, and the cached pointer indicates the entry point of that single method.

摘要翻译： 公开了一种面向对象的处理器和操作这种处理器的方法。 根据该方法，响应于接收到引用具有数据的第一对象和至少与其相关联的第一方法的第一对象的第一指令，计算第一方法的地址。 另外，至少一个指针被缓存，指示（可能与其他指针一起）第一个方法的地址。 响应于接收到引用具有两个数据的第二对象以及与其相关联的一个或多个方法的随后的第二指令，其中一个或多个方法包括第一方法，与第二对象相关联的第二方法的地址由 引用缓存的指针。 在本发明的优选实施例中，第一和第二方法包括相同的方法，并且缓存的指针指示该单一方法的入口点。

公开(公告)号：US6070173A

公开(公告)日：2000-05-30

申请号：US979595

申请日：1997-11-26

申请人： Gary Douglas Huber ,  Donald William McCauley

发明人： Gary Douglas Huber ,  Donald William McCauley

IPC分类号： G06F12/02 ,  G06F17/30

CPC分类号： G06F12/0253 ,  Y10S707/99957

摘要： A method and apparatus for assisting garbage collection process within a Java virtual machine are disclosed. A virtual object heap and a physical object heap are provided within the Java virtual machine, with the virtual object heap considerably larger than the physical object heap. Objects from Java applications are allocated within the virtual object heap. Each address of the allocated objects within the virtual object heap is translated into an address of a location within the physical object heap. Garbage collection is performed in the virtual object heap only when a total number of objects within the virtual object heap has reached a predetermined threshold.

摘要翻译： 公开了一种在Java虚拟机内辅助垃圾收集过程的方法和装置。 虚拟对象堆和物理对象堆在Java虚拟机中提供，虚拟对象堆大大超过物理堆。 来自Java应用程序的对象在虚拟对象堆中分配。 虚拟对象堆内分配的对象的每个地址都将被转换为物理对象堆内某个位置的地址。 仅当虚拟对象堆中的对象总数达到预定阈值时，才会在虚拟对象堆中执行垃圾收集。