公开(公告)号：US20080091810A1

公开(公告)日：2008-04-17

申请号：US11550079

申请日：2006-10-17

申请人： Katherine Tyldesley Blinick ,  Rezaul Shah Mohammad Islam ,  Gregg Steven Lucas ,  Robert Earl Medlin ,  Tohru Sumiyoshi

发明人： Katherine Tyldesley Blinick ,  Rezaul Shah Mohammad Islam ,  Gregg Steven Lucas ,  Robert Earl Medlin ,  Tohru Sumiyoshi

IPC分类号： G06F15/173

CPC分类号： H04L67/1097 ,  H04L49/10 ,  H04L49/30 ,  H04L49/40 ,  H04L49/45

摘要： A high speed fabric is provided and is partitioned into sub-fabrics for host adapter traffic and device adapter traffic. A high-speed switch includes an expander for host adapter traffic and an expander for device adapter traffic. The high-speed switch also includes a plurality of connectors, where each connector is partitioned into dual interfaces. For each connector, one interface is connected to the host adapter traffic expander and the other interface is connected to the device adapter traffic expander. Blades are provided with one or more connectors, where each connector is partitioned into dual interfaces for host adapter traffic and device adapter traffic. The blades may be any combination of processor blades, boot drive enclosure blades, switched bunch of disks enclosure blades, and/or integrated RAID controller disk enclosure blades.

摘要翻译： 提供了高速架构，并将其划分为用于主机适配器流量和设备适配器流量的子架构。 高速交换机包括用于主机适配器流量的扩展器和用于设备适配器流量的扩展器。 高速开关还包括多个连接器，其中每个连接器被分成双重接口。 对于每个连接器，一个接口连接到主机适配器流量扩展器，另一个接口连接到设备适配器流量扩展器。 刀片具有一个或多个连接器，其中每个连接器被分割成用于主机适配器业务和设备适配器业务的双接口。 刀片可以是处理器刀片，引导驱动器机箱刀片，交换机磁盘阵列刀片和/或集成的RAID控制器磁盘机箱刀片的任何组合。

公开(公告)号：US07787482B2

公开(公告)日：2010-08-31

申请号：US11550079

申请日：2006-10-17

申请人： Katherine Tyldesley Blinick ,  Rezaul Shah Mohammad Islam ,  Gregg Steven Lucas ,  Robert Earl Medlin ,  Tohru Sumiyoshi

发明人： Katherine Tyldesley Blinick ,  Rezaul Shah Mohammad Islam ,  Gregg Steven Lucas ,  Robert Earl Medlin ,  Tohru Sumiyoshi

IPC分类号： H04L12/28

CPC分类号： H04L67/1097 ,  H04L49/10 ,  H04L49/30 ,  H04L49/40 ,  H04L49/45

摘要： A high speed fabric is provided and is partitioned into sub-fabrics for host adapter traffic and device adapter traffic. A high-speed switch includes an expander for host adapter traffic and an expander for device adapter traffic. The high-speed switch also includes a plurality of connectors, where each connector is partitioned into dual interfaces. For each connector, one interface is connected to the host adapter traffic expander and the other interface is connected to the device adapter traffic expander. Blades are provided with one or more connectors, where each connector is partitioned into dual interfaces for host adapter traffic and device adapter traffic. The blades may be any combination of processor blades, boot drive enclosure blades, switched bunch of disks enclosure blades, and/or integrated RAID controller disk enclosure blades.

摘要翻译： 提供了高速架构，并将其划分为用于主机适配器流量和设备适配器流量的子架构。 高速交换机包括用于主机适配器流量的扩展器和用于设备适配器流量的扩展器。 高速开关还包括多个连接器，其中每个连接器被分成双重接口。 对于每个连接器，一个接口连接到主机适配器流量扩展器，另一个接口连接到设备适配器流量扩展器。 刀片具有一个或多个连接器，其中每个连接器被分割成用于主机适配器业务和设备适配器业务的双接口。 刀片可以是处理器刀片，引导驱动器机箱刀片，交换机磁盘阵列刀片和/或集成的RAID控制器磁盘机箱刀片的任何组合。

公开(公告)号：US20080046647A1

公开(公告)日：2008-02-21

申请号：US11464701

申请日：2006-08-15

申请人： Katherine Tyldesley Blinick ,  Shah Mohammad Rezaul Islam ,  Gregg Steven Lucas ,  Robert Earl Medlin

发明人： Katherine Tyldesley Blinick ,  Shah Mohammad Rezaul Islam ,  Gregg Steven Lucas ,  Robert Earl Medlin

IPC分类号： G06F12/16 ,  G06F12/14

CPC分类号： G06F3/0658 ,  G06F3/0626 ,  G06F3/067 ,  G06F3/0689 ,  H04L67/1097

摘要： An apparatus, system, and method are disclosed for integrating redundant array of independent disk (“RAID”) storage within a blade center. A plurality of mutually autonomous storage subsystems mount within the blade center through a switch. Each storage subsystem includes a storage module comprising a plurality of storage devices and a RAID controller. A server blade mounted within the blade center may access a first storage subsystem through a switch module. The switch module is a non-blocking, cross-point switch. In one embodiment, the switch module restricts the server blade's access to a second storage subsystem.

摘要翻译： 公开了用于在刀片中心内集成独立盘（“RAID”）冗余阵列的装置，系统和方法。 多个相互独立的存储子系统通过开关安装在刀片中心内。 每个存储子系统包括包括多个存储设备和RAID控制器的存储模块。 安装在刀片中心内的服务器刀片可以通过开关模块访问第一个存储子系统。 交换机模块是一个非阻塞交叉点交换机。 在一个实施例中，交换机模块限制服务器刀片对第二存储子系统的访问。

公开(公告)号：US07546415B2

公开(公告)日：2009-06-09

申请号：US11464701

申请日：2006-08-15

申请人： Katherine Tyldesley Blinick ,  Shah Mohammad Rezaul Islam ,  Gregg Steven Lucas ,  Robert Earl Medlin

发明人： Katherine Tyldesley Blinick ,  Shah Mohammad Rezaul Islam ,  Gregg Steven Lucas ,  Robert Earl Medlin

IPC分类号： G06F12/00

CPC分类号： G06F3/0658 ,  G06F3/0626 ,  G06F3/067 ,  G06F3/0689 ,  H04L67/1097

摘要： An apparatus, system, and method are disclosed for integrating redundant array of independent disk (“RAID”) storage within a blade center. A plurality of mutually autonomous storage subsystems mount within the blade center through a switch. Each storage subsystem includes a storage module comprising a plurality of storage devices and a RAID controller. A server blade mounted within the blade center may access a first storage subsystem through a switch module. The switch module is a non-blocking, cross-point switch. In one embodiment, the switch module restricts the server blade's access to a second storage subsystem.

摘要翻译： 公开了用于在刀片中心内集成独立盘（“RAID”）冗余阵列的装置，系统和方法。 多个相互独立的存储子系统通过交换机安装在刀片中心内。 每个存储子系统包括包括多个存储设备和RAID控制器的存储模块。 安装在刀片中心内的服务器刀片可以通过开关模块访问第一个存储子系统。 交换机模块是一个非阻塞交叉点交换机。 在一个实施例中，交换机模块限制服务器刀片对第二存储子系统的访问。

公开(公告)号：US07020809B2

公开(公告)日：2006-03-28

申请号：US10255040

申请日：2002-09-25

申请人： Yvonne Hanson Kleppel ,  Russell Lee Ellison ,  Enrique Garcia ,  Rajendrasinh Banesinh Jadeja ,  Gregg Steven Lucas ,  Robert Earl Medlin

发明人： Yvonne Hanson Kleppel ,  Russell Lee Ellison ,  Enrique Garcia ,  Rajendrasinh Banesinh Jadeja ,  Gregg Steven Lucas ,  Robert Earl Medlin

IPC分类号： G06F11/00

CPC分类号： H04L12/4013 ,  H04L12/403 ,  H04L69/40

摘要： A system and method for verifying integrity of data signals communicated from a data transmit device to a receive device over a communications channel of limited bandwidth. The method comprising steps of: a) detecting instances of idle data transmit activity at the transmit device; b) accumulating data integrity information for data transmitted over the communication channel between detected idle transmit instances, the accumulating being performed by data integrity verifier devices at both transmit and receive devices; c) communicating accumulated data integrity information for data transmitted since a last detected idle data transmit instance during a current detected idle data transmit instance; and, d) verifying accumulated data integrity information communicated over the channel at the receiver device. The system and method of the invention may be used to provide intermediate data integrity checks when communication of packets belonging to a stream is interrupted without compromising bandwidth utilization. Moreover, the system and method of the invention may be used to provide data integrity verification for data communicated over two or more communications channels between instances of detected idle transmit states.

摘要翻译： 一种用于验证通过有限带宽的通信信道从数据发送设备传送到接收设备的数据信号的完整性的系统和方法。 该方法包括以下步骤：a）检测发送设备处的空闲数据发送活动的实例; b）累积针对在所检测到的空闲发送实例之间通过通信信道发送的数据的数据完整性信息，所述累积由数据完整性验证器在发送和接收设备两者执行; c）在当前检测到的空闲数据发送实例期间，传送从上次检测到的空闲数据发送实例以来发送的数据的累积数据完整性信息; 以及d）验证在所述接收机设备处通过所述信道传送的累积数据完整性信息。 当属于流的分组的通信被中断而不影响带宽利用时，本发明的系统和方法可用于提供中间数据完整性检查。 此外，本发明的系统和方法可以用于为在检测到的空闲发送状态的实例之间的两个或多个通信信道上传送的数据提供数据完整性验证。

公开(公告)号：US06449678B1

公开(公告)日：2002-09-10

申请号：US09275470

申请日：1999-03-24

申请人： Gary William Batchelor ,  Russell Lee Ellison ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Forrest Lee Wade ,  Juan Antonio Yanes

发明人： Gary William Batchelor ,  Russell Lee Ellison ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Forrest Lee Wade ,  Juan Antonio Yanes

IPC分类号： G06F1300

CPC分类号： G06F13/4027

摘要： Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.

摘要翻译： 公开了一种用于通过总线处理来自多个代理的读/写交易的系统。 该桥包括与桥接通信的每个代理的至少一个请求缓冲器。 代理的请求缓冲区缓冲来自该代理的事务。 桥接器还包括与桥接器通信的每个代理的返回缓冲器。 代理缓冲区缓冲区返回与事务相关的数据。 地址转换电路与总线通信，请求和返回缓冲器。 地址转换电路定位请求缓冲器以对事务进行排队，使得事务存储在与发起事务的代理相对应的请求缓冲器中。 此外，地址转换电路将用于读取事务的读取返回数据存储在与发起事务的代理相对应的返回缓冲器中。

公开(公告)号：US06425023B1

公开(公告)日：2002-07-23

申请号：US09275603

申请日：1999-03-24

申请人： Gary William Batchelor ,  Carl Evan Jones ,  Dell Patrick Leabo ,  Robert Earl Medlin ,  Forrest Lee Wade

发明人： Gary William Batchelor ,  Carl Evan Jones ,  Dell Patrick Leabo ,  Robert Earl Medlin ,  Forrest Lee Wade

IPC分类号： G06F1314

CPC分类号： G06F13/4027

摘要： Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent. In a similar manner, in delayed write operations, the write data may also be gathered from several write operations and assembled into an address boundary-aligned block of write data before the bridge circuit forwards the write data to the target device.

摘要翻译： 公开了一种用于通过总线处理读和写交易的桥接系统，其中在优选实施例中，通过辅助总线在多个单独的读取操作中从目标设备获得的连续读取数据可以由桥梁收集并组装成更大的 在通过主总线将数据转发到请求代理之前的数据块。 因此，可以增加在主总线上传输读取数据的最佳地址边界对准突发，相反地，可以减少通过主总线的分级，非对齐读取数据的传输。 由于每个代理被分配特定的缓冲区，读取数据可以在分配的桥接缓冲器中同时收集，而不会由一个代理导致对不同代理收集的数据的刷新的读取请求。 以类似的方式，在延迟写入操作中，也可以从桥接电路将写入数据转发到目标设备之前，从多个写入操作中收集写入数据并将其组合成写入数据的地址边界对齐块。

公开(公告)号：US06636913B1

公开(公告)日：2003-10-21

申请号：US09551861

申请日：2000-04-18

申请人： Gary William Batchelor ,  Michael Thomas Benhase ,  Joseph Smith Hyde, II ,  Robert Earl Medlin ,  Juan Antonio Yanes

发明人： Gary William Batchelor ,  Michael Thomas Benhase ,  Joseph Smith Hyde, II ,  Robert Earl Medlin ,  Juan Antonio Yanes

IPC分类号： G06F1300

CPC分类号： G06F13/126

摘要： A method and system for controlling access to a bus for transferring data in the form of multibyte data streams. Data transfer agents are coupled to and request access to the bus to transfer data thereon. The system for controlling access to the bus comprises a bus arbiter responsive to the access requests of the data transfer agents, granting access to the bus to one data transfer agent at a time. A data length counter accumulates, during the grant of access, signals indicating the length of the data transferred between the bus and the data transfer agent. The data length counter indicates completion of the transfer of a predetermined length of data, and bus arbiter logic responds to the data length counter indicating the transfer completion, causing the bus arbiter to terminate the grant of access to the data transfer agent. The control of access to the bus is thus based on the precise measurement of the length of the transferred data, rather than on timers.

摘要翻译： 一种用于控制访问总线以用于以多字节数据流的形式传送数据的方法和系统。 数据传输代理被耦合到请求访问总线以在其上传送数据。 用于控制对总线的访问的系统包括响应于数据传输代理的访问请求的总线仲裁器，一次授予对一个数据传输代理的总线访问。 在授权访问期间，数据长度计数器累积指示在总线和数据传送代理之间传送的数据的长度的信号。 数据长度计数器指示传输预定长度的数据的完成，并且总线仲裁器逻辑响应指示传送完成的数据长度计数器，导致总线仲裁器终止对数据传输代理的访问许可。 因此，对总线访问的控制基于精确测量传输数据的长度，而不是基于定时器。

公开(公告)号：US06490644B1

公开(公告)日：2002-12-03

申请号：US09521387

申请日：2000-03-08

申请人： Joseph Smith Hyde, II ,  Robert Earl Medlin ,  Juan Antonio Yanes

发明人： Joseph Smith Hyde, II ,  Robert Earl Medlin ,  Juan Antonio Yanes

IPC分类号： G06F13372

CPC分类号： G06F13/362

摘要： A system for limiting fracturing of write data by a PCI bus adapter which queues operation commands in a command queue. The write data is in the form of bursts comprising a plurality of contiguous words. Fracture detection logic senses fracturing of the write data. A bus arbiter is responsive to the sensed fracturing of write data by the target, and blocks access to the PCI bus. Queue level detection logic is employed, subsequent to the blocking, to monitor completion of the queued operation commands of the PCI bus target. The bus arbiter is then responsive to the queue level detection logic indicating that the PCI bus target has completed enough operations that a predetermined number (such as one) of the operation commands remain queued at its command queue, and grants access to the PCI bus to complete the burst write operation without fracturing.

摘要翻译： 用于通过PCI总线适配器限制写数据压缩的系统，其将命令队列中的操作命令排队。 写数据是包括多个连续字的突发的形式。 断裂检测逻辑检测写入数据的压裂。 总线仲裁器响应于由目标感测到的写入数据的压缩，并阻止对PCI总线的访问。 在阻塞之后采用队列级检测逻辑来监视PCI总线目标的排队操作命令的完成。 总线仲裁器然后响应于队列等级检测逻辑，指示PCI总线目标已经完成足够的操作，其中预定数量（诸如一个）操作命令在其命令队列中保持排队，并且授予对PCI总线的访问 完成突发写入操作而不破裂。

公开(公告)号：US06189117B1

公开(公告)日：2001-02-13

申请号：US09135835

申请日：1998-08-18

申请人： Gary William Batchelor ,  Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Jack Harvey Derenburger ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Juan Antonio Yanes

发明人： Gary William Batchelor ,  Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Jack Harvey Derenburger ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Juan Antonio Yanes

IPC分类号： G06F1100

CPC分类号： G06F11/0796

摘要： Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.

摘要翻译： 公开了一种处理错误的系统。 由处理器管理的系统处理系统中的错误。 系统然后在处理器解释中断之前，向处理器产生指示发生错误的中断并执行错误模式。 作为错误模式的一部分，系统防止数据在系统和处理器之间传输，并通过将数据返回到与请求的数据无关的处理器来处理从处理器到系统的读取请求。 然后处理器将处理指示错误的中断，并执行诊断模式以诊断系统中的错误。