公开(公告)号：US06636913B1

公开(公告)日：2003-10-21

申请号：US09551861

申请日：2000-04-18

申请人： Gary William Batchelor ,  Michael Thomas Benhase ,  Joseph Smith Hyde, II ,  Robert Earl Medlin ,  Juan Antonio Yanes

发明人： Gary William Batchelor ,  Michael Thomas Benhase ,  Joseph Smith Hyde, II ,  Robert Earl Medlin ,  Juan Antonio Yanes

IPC分类号： G06F1300

CPC分类号： G06F13/126

摘要： A method and system for controlling access to a bus for transferring data in the form of multibyte data streams. Data transfer agents are coupled to and request access to the bus to transfer data thereon. The system for controlling access to the bus comprises a bus arbiter responsive to the access requests of the data transfer agents, granting access to the bus to one data transfer agent at a time. A data length counter accumulates, during the grant of access, signals indicating the length of the data transferred between the bus and the data transfer agent. The data length counter indicates completion of the transfer of a predetermined length of data, and bus arbiter logic responds to the data length counter indicating the transfer completion, causing the bus arbiter to terminate the grant of access to the data transfer agent. The control of access to the bus is thus based on the precise measurement of the length of the transferred data, rather than on timers.

摘要翻译： 一种用于控制访问总线以用于以多字节数据流的形式传送数据的方法和系统。 数据传输代理被耦合到请求访问总线以在其上传送数据。 用于控制对总线的访问的系统包括响应于数据传输代理的访问请求的总线仲裁器，一次授予对一个数据传输代理的总线访问。 在授权访问期间，数据长度计数器累积指示在总线和数据传送代理之间传送的数据的长度的信号。 数据长度计数器指示传输预定长度的数据的完成，并且总线仲裁器逻辑响应指示传送完成的数据长度计数器，导致总线仲裁器终止对数据传输代理的访问许可。 因此，对总线访问的控制基于精确测量传输数据的长度，而不是基于定时器。

公开(公告)号：US06189117B1

公开(公告)日：2001-02-13

申请号：US09135835

申请日：1998-08-18

申请人： Gary William Batchelor ,  Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Jack Harvey Derenburger ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Juan Antonio Yanes

发明人： Gary William Batchelor ,  Brent Cameron Beardsley ,  Michael Thomas Benhase ,  Jack Harvey Derenburger ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Juan Antonio Yanes

IPC分类号： G06F1100

CPC分类号： G06F11/0796

摘要： Disclosed is a system for handling errors. A system managed by a processor processes an error in the system. The system then generates an interrupt to the processor indicating that an error occurred and executes an error mode before the processor interprets the interrupt. As part of the error mode, the system prevents data from transferring between the system and the processor and processes a read request from the processor to the system by returning data to the processor unrelated to the requested data. The processor would then process the interrupt indicating the error and execute a diagnostic mode to diagnose the error in the system.

摘要翻译： 公开了一种处理错误的系统。 由处理器管理的系统处理系统中的错误。 系统然后在处理器解释中断之前，向处理器产生指示发生错误的中断并执行错误模式。 作为错误模式的一部分，系统防止数据在系统和处理器之间传输，并通过将数据返回到与请求的数据无关的处理器来处理从处理器到系统的读取请求。 然后处理器将处理指示错误的中断，并执行诊断模式以诊断系统中的错误。

公开(公告)号：US06449678B1

公开(公告)日：2002-09-10

申请号：US09275470

申请日：1999-03-24

申请人： Gary William Batchelor ,  Russell Lee Ellison ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Forrest Lee Wade ,  Juan Antonio Yanes

发明人： Gary William Batchelor ,  Russell Lee Ellison ,  Carl Evan Jones ,  Robert Earl Medlin ,  Belayneh Tafesse ,  Forrest Lee Wade ,  Juan Antonio Yanes

IPC分类号： G06F1300

CPC分类号： G06F13/4027

摘要： Disclosed is a system for processing read/write transactions from a plurality of agents over a bus. The bridge includes at least one request buffer for each agent in communication with the bridge. The request buffer for an agent buffers transactions originating from that agent. The bridge further includes a return buffer for each agent in communication with the bridge. The return buffer for an agent buffers return data in connection with a transaction. Address translation circuitry is in communication with the bus and request and return buffers. The address translation circuitry locates a request buffer to queue the transaction, such that a transaction is stored in the request buffer corresponding to the agent that originated the transaction. Further, the address translation circuitry stores read return data for a read transaction in the return buffer corresponding to the agent originating the transaction.

摘要翻译： 公开了一种用于通过总线处理来自多个代理的读/写交易的系统。 该桥包括与桥接通信的每个代理的至少一个请求缓冲器。 代理的请求缓冲区缓冲来自该代理的事务。 桥接器还包括与桥接器通信的每个代理的返回缓冲器。 代理缓冲区缓冲区返回与事务相关的数据。 地址转换电路与总线通信，请求和返回缓冲器。 地址转换电路定位请求缓冲器以对事务进行排队，使得事务存储在与发起事务的代理相对应的请求缓冲器中。 此外，地址转换电路将用于读取事务的读取返回数据存储在与发起事务的代理相对应的返回缓冲器中。

公开(公告)号：US06425023B1

公开(公告)日：2002-07-23

申请号：US09275603

申请日：1999-03-24

申请人： Gary William Batchelor ,  Carl Evan Jones ,  Dell Patrick Leabo ,  Robert Earl Medlin ,  Forrest Lee Wade

发明人： Gary William Batchelor ,  Carl Evan Jones ,  Dell Patrick Leabo ,  Robert Earl Medlin ,  Forrest Lee Wade

IPC分类号： G06F1314

CPC分类号： G06F13/4027

摘要： Disclosed is a bridge system for processing read and write transactions over a bus in which in a preferred embodiment continuous read data obtained from a target device in a number of separate read operations over a secondary bus may be gathered by the bridge and assembled into a larger block of data before forwarding the data over the primary bus to the requesting agent. As a consequence, the transmission of optimal, address boundary-aligned bursts of read data over the primary bus may be increased and conversely, the transmission of fractionated, nonaligned read data over the primary bus may be reduced. Because each agent is assigned particular buffers, read data may be gathered concurrently in the assigned bridge buffers without assertion of a read request by one agent causing the flushing of the data being gathered for a different agent. In a similar manner, in delayed write operations, the write data may also be gathered from several write operations and assembled into an address boundary-aligned block of write data before the bridge circuit forwards the write data to the target device.

摘要翻译： 公开了一种用于通过总线处理读和写交易的桥接系统，其中在优选实施例中，通过辅助总线在多个单独的读取操作中从目标设备获得的连续读取数据可以由桥梁收集并组装成更大的 在通过主总线将数据转发到请求代理之前的数据块。 因此，可以增加在主总线上传输读取数据的最佳地址边界对准突发，相反地，可以减少通过主总线的分级，非对齐读取数据的传输。 由于每个代理被分配特定的缓冲区，读取数据可以在分配的桥接缓冲器中同时收集，而不会由一个代理导致对不同代理收集的数据的刷新的读取请求。 以类似的方式，在延迟写入操作中，也可以从桥接电路将写入数据转发到目标设备之前，从多个写入操作中收集写入数据并将其组合成写入数据的地址边界对齐块。

公开(公告)号：US07051223B2

公开(公告)日：2006-05-23

申请号：US10677152

申请日：2003-09-30

申请人： Gary William Batchelor ,  Michael Thomas Benhase ,  Enrique Garcia ,  Carl Evan Jones ,  Trung Le

发明人： Gary William Batchelor ,  Michael Thomas Benhase ,  Enrique Garcia ,  Carl Evan Jones ,  Trung Le

IPC分类号： G06F12/16

CPC分类号： G06F11/1441

摘要： An apparatus for limiting volatile computer memory based on available energy in an auxiliary power source comprises an energy monitor module configured to determine an amount of available energy in the auxiliary power source. Also provided is a memory status module configured to determine an amount of volatile computer memory allocated for use in a computer and a memory adjustment module configured to adjust the amount of volatile computer memory allocated for use in the computer based on the amount of available energy in the auxiliary power source. A startup module may be configured to allow the computer to begin moving data normally when the memory adjustment module limits volatile computer memory allocated for use by the computer to a minimum level and the energy monitor module determines that the amount of available energy in the auxiliary power source has reached a minimum level capable of transferring the volatile computer memory allocated for use by the computer to non-volatile computer memory during a computer shutdown.

摘要翻译： 基于辅助电源中的可用能量来限制易失性计算机存储器的装置包括被配置为确定辅助电源中的可用能量的能量监测模块。 还提供了一种存储器状态模块，其被配置为确定分配用于计算机的易失性计算机存储器的量和存储器调整模块，所述存储器调整模块被配置为基于可用能量的量来调整分配用于计算机中的易失性计算机存储器的数量 辅助电源。 启动模块可以被配置为当存储器调整模块将分配供计算机使用的易失性计算机存储器限制在最小水平时允许计算机开始正常地移动数据，并且能量监视器模块确定辅助功率中的可用能量的量 源已经达到能够在计算机关闭期间将分配给计算机使用的易失性计算机存储器传送到非易失性计算机存储器的最小级别。

公开(公告)号：US06490647B1

公开(公告)日：2002-12-03

申请号：US09542917

申请日：2000-04-04

申请人： Gary William Batchelor ,  Michael Thomas Benhase

发明人： Gary William Batchelor ,  Michael Thomas Benhase

IPC分类号： G06F1336

CPC分类号： G06F13/4059

摘要： A system and method for flushing stale data from a read prefetch buffer of a PCI bus system which transfers data in the form of data streams of contiguous blocks. The PCI bus system comprises a channel adapter at one PCI bus that issues read commands, a data source coupled to a second PCI bus, and a prefetch buffer that prefetches the blocks of read data. A prefetch counter posts the remaining number blocks to be read and transferred, posting the prefetch count at a storage location of a storage memory mapped to a prefetch location in the prefetch buffer. The prefetch count is written to the storage location by a prefetch count write command. The system for flushing stale data from the prefetch buffer comprises a key detector for sensing an unique identifier of the prefetch count write command. Data path logic responds to the key detector, determining the prefetch location of the prefetch buffer from the mapped storage location of the prefetch count write command, and flushing any prefetch data at the determined prefetch location.

摘要翻译： 用于从PCI总线系统的读取预取缓冲器中刷新过期数据的系统和方法，其以连续块的数据流的形式传送数据。 PCI总线系统包括在一个PCI总线处发出读命令的通道适配器，耦合到第二PCI总线的数据源，以及预读取数据块的预取缓冲器。 预取计数器发布要读取和传送的剩余数字块，在预取缓冲器中映射到预取位置的存储存储器的存储位置发布预取计数。 预取计数通过预取计数写入命令写入存储位置。 用于从预取缓冲器冲洗过期数据的系统包括用于感测预取计数写入命令的唯一标识符的密钥检测器。 数据路径逻辑响应密钥检测器，从预取计数写入命令的映射存储位置确定预取缓冲器的预取位置，以及在确定的预取位置处刷新任何预取数据。

公开(公告)号：US06578102B1

公开(公告)日：2003-06-10

申请号：US09551862

申请日：2000-04-18

申请人： Gary William Batchelor ,  Michael Thomas Benhase

发明人： Gary William Batchelor ,  Michael Thomas Benhase

IPC分类号： G06F1300

CPC分类号： G06F13/4059

摘要： A system and method track and control the prefetching of blocks of a data stream in a PCI bus system, avoiding unnecessary prefetches. The data stream is grouped into major blocks which comprise a fixed plurality of contiguous blocks. A prefetch buffer stores the blocks of data prefetched from a PCI data source for transfer to a requester. First and second associated prefetch count storage locations store first and second counts initialized by prefetch initialization logic. The first count represents the number of blocks of data of a major block of the data, and the second count represents the total number of the blocks of the data stream to be prefetched, less the initialized number of blocks of the first count. As each block of data is prefetched, a prefetch counter decrements the first count by a number representing the block of data. As the prefetch counter decrements the first count to zero, prefetch count logic stops the prefetch, allowing completion of the transfer of the prefetched data to the data destination. Thus, the second count represents the next remaining number of blocks to be prefetched, and the requester can rotate to a different read request at the end of a major block, knowing the next major block will not be prefetched until requested.

摘要翻译： 系统和方法跟踪和控制PCI总线系统中数据流块的预取，避免不必要的预取。 数据流被分组成包括固定的多个相邻块的主要块。 预取缓冲器将从PCI数据源预取的数据块存储到请求者。 第一和第二相关联的预取计数存储位置存储通过预取初始化逻辑初始化的第一和第二计数。 第一计数表示数据的主要块的数据块的数量，第二计数表示要预取的数据流的块的总数，少于初始数的块的初始化数。 当每个数据块被预取时，预取计数器将第一个计数器递减一个表示数据块的数字。 当预取计数器将第一计数器递减到零时，预取计数逻辑停止预取，从而允许完成将预取数据传送到数据目的地。 因此，第二计数表示要预取的块的下一个剩余数量，并且请求者可以在主块的结尾处旋转到不同的读请求，知道下一个主块将不被预取，直到被请求为止。

公开(公告)号：US20080074280A1

公开(公告)日：2008-03-27

申请号：US11535367

申请日：2006-09-26

申请人： Gary William Batchelor ,  Brian James Cagno ,  Yolanda Colpo ,  Enrique Garcia

发明人： Gary William Batchelor ,  Brian James Cagno ,  Yolanda Colpo ,  Enrique Garcia

IPC分类号： G09F9/33

CPC分类号： H05B33/0863 ,  H05B37/0254

摘要： An apparatus, system, and method are disclosed for dual master LED (Light Emitting Diode) control. Two hosts are connected to and redundantly control the operation of an LED. Communication modules coupled to the two hosts facilitate communication between the two hosts without affecting the normal operation of the LED. This is done by sending pulses between the two hosts such that the hosts can be synchronized as well as communicate information to one another across the LED channel. The pulses have a small width such that any affect on the LED is imperceptible to humans.

摘要翻译： 公开了用于双主LED（发光二极管）控制的装置，系统和方法。 两个主机连接并冗余控制LED的操作。 耦合到两个主机的通信模块有助于两台主机之间的通信，而不会影响LED的正常运行。 这通过在两个主机之间发送脉冲来实现，使得主机可以同步并且在LED通道上彼此通信信息。 脉冲具有小的宽度，使得对于LED的任何影响对于人来说是不可察觉的。

公开(公告)号：US06286074B1

公开(公告)日：2001-09-04

申请号：US09275610

申请日：1999-03-24

申请人： Gary William Batchelor ,  Brent Cameron Beardsley ,  Matthew Joseph Kalos ,  Forrest Lee Wade

发明人： Gary William Batchelor ,  Brent Cameron Beardsley ,  Matthew Joseph Kalos ,  Forrest Lee Wade

IPC分类号： G06F1314

CPC分类号： G06F13/4059

摘要： Disclosed is a bridge system for processing read transactions over a bus in which in a preferred embodiment prefetched data stored in a buffer is not discarded if the address of the requested read does not match the beginning address of the prefetched data. Instead, the bridge system skips to the next address of the prefetched data stored in the buffer and compares that address to the address of the read request to determine if a match exists. If the requested read address does match the next prefetched data address, the prefetched data starting at that next address is read out and forwarded to the requesting agent. Alternatively, if there is not a match, the bridge skips again to the next address and continues checking for a match until either the prefetched data is exhausted or another predetermined limit has been reached. In this manner, many unnecessary data reads of data already prefetched in the buffer may be avoided.

摘要翻译： 公开了一种用于通过总线处理读取事务的桥接系统，其中在优选实施例中，如果所请求的读取的地址与预取数据的起始地址不匹配，则不会丢弃存储在缓冲器中的预取数据。 相反，桥接系统跳过存储在缓冲器中的预取数据的下一个地址，并将该地址与读取请求的地址进行比较，以确定是否存在匹配。 如果所请求的读取地址与下一个预取数据地址匹配，则从该下一个地址开始的预取数据被读出并转发给请求代理。 或者，如果不匹配，桥接器再次跳到下一个地址，并继续检查匹配，直到预取的数据被耗尽或达到了另一个预定的限制。 以这种方式，可以避免在缓冲器中预取的数据的许多不必要的数据读取。

公开(公告)号：US07685325B2

公开(公告)日：2010-03-23

申请号：US11969351

申请日：2008-01-04

申请人： Gary William Batchelor ,  Enrique Garcia

发明人： Gary William Batchelor ,  Enrique Garcia

IPC分类号： G06F13/00

CPC分类号： G06F13/4217

摘要： A system for generating bus signals for a plurality of remote stations. Bus data packets are comprised of a plurality of data blocks. Each data block is directed to a remote station. The position of each data block in the data packet identifies the remote station to which the data block is directed. Each of the remote stations receives each data packet substantially synchronously. The remote stations decode the data packets to determine the type of data packet and identify the content of the data packet directed to it. Each remote station loads the corresponding content from the data packet. Each of the remote stations can then generate output signals based on the data packet content substantially synchronously with the other remote stations.

摘要翻译： 一种用于生成多个远程站的总线信号的系统。 总线数据分组由多个数据块组成。 每个数据块被定向到远程站。 数据包中每个数据块的位置标识数据块所针对的远程站。 每个远程站基本同步地接收每个数据分组。 远程站对数据分组进行解码以确定数据分组的类型并识别指向其的数据分组的内容。 每个远程站从数据包中加载相应的内容。 然后，每个远程站可以基于与其他远程站基本上同步的数据分组内容生成输出信号。