公开(公告)号：US20060038215A1

公开(公告)日：2006-02-23

申请号：US11256929

申请日：2005-10-25

申请人： Katsuaki Natori ,  Tomohiro Saito ,  Yoshihiro Vozumi

发明人： Katsuaki Natori ,  Tomohiro Saito ,  Yoshihiro Vozumi

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  H01L21/76807 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrode.

公开(公告)号：US07405133B2

公开(公告)日：2008-07-29

申请号：US11256929

申请日：2005-10-25

申请人： Katsuaki Natori ,  Tomohiro Saito ,  Yoshihiro Uozumi

发明人： Katsuaki Natori ,  Tomohiro Saito ,  Yoshihiro Uozumi

IPC分类号： H01L21/20

CPC分类号： H01L28/55 ,  H01L21/76807 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrode.

摘要翻译： 一种半导体器件，包括半导体衬底和形成在半导体衬底上的多个电容器。 电容器包括形成在半导体衬底上的多个下电极，连续地覆盖多个下电极的铁电膜和形成在铁电体膜的表面上的上电极，其中形成每个电容器 多个下电极。

公开(公告)号：US07022580B2

公开(公告)日：2006-04-04

申请号：US10222813

申请日：2002-08-19

申请人： Katsuaki Natori ,  Tomohiro Saito ,  Yoshihiro Uozumi

发明人： Katsuaki Natori ,  Tomohiro Saito ,  Yoshihiro Uozumi

IPC分类号： H01L21/20

CPC分类号： H01L28/55 ,  H01L21/76807 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrodes.

摘要翻译： 一种半导体器件，包括半导体衬底和形成在半导体衬底上的多个电容器。 电容器包括形成在半导体衬底上的多个下电极，连续地覆盖多个下电极的铁电膜和形成在铁电体膜的表面上的上电极，其中形成每个电容器 多个下电极。

公开(公告)号：US06459111B1

公开(公告)日：2002-10-01

申请号：US09609712

申请日：2000-06-30

申请人： Katsuaki Natori ,  Tomohiro Saito ,  Yoshihiro Uozumi

发明人： Katsuaki Natori ,  Tomohiro Saito ,  Yoshihiro Uozumi

IPC分类号： H01L2972

CPC分类号： H01L28/55 ,  H01L21/76807 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

摘要： A semiconductor device comprising a semiconductor substrate, and a plurality of capacitors formed on the semiconductor substrate. The capacitors comprise a plurality of lower electrodes formed on the semiconductor substrate, a ferroelectric film formed continuously covering the plurality of lower electrodes, and an upper electrode formed on the surface of the ferroelectric film, wherein each of the capacitors is formed for each of the plurality of lower electrode.

摘要翻译： 一种半导体器件，包括半导体衬底和形成在半导体衬底上的多个电容器。 电容器包括形成在半导体衬底上的多个下电极，连续地覆盖多个下电极的铁电膜和形成在铁电体膜的表面上的上电极，其中形成每个电容器 多个下电极。

公开(公告)号：US08741161B2

公开(公告)日：2014-06-03

申请号：US13428535

申请日：2012-03-23

申请人： Yasuyuki Sonoda ,  Kyoichi Suguro ,  Masatoshi Yoshikawa ,  Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno

发明人： Yasuyuki Sonoda ,  Kyoichi Suguro ,  Masatoshi Yoshikawa ,  Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno

IPC分类号： H01L21/302

CPC分类号： H01L21/31053 ,  H01L27/228 ,  H01L43/12

摘要： According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.

摘要翻译： 根据一个实施方案，一种制造半导体器件的方法，该方法包括在基底层上形成柱，在基底层上形成绝缘层以通过GCIB法覆盖柱，其中上表面的最下部分 绝缘层低于柱的上表面，并且通过使用CMP方法研磨绝缘层和柱以露出柱的头部，其中抛光的终点是上表面的最下部 绝缘层。

公开(公告)号：US08604573B2

公开(公告)日：2013-12-10

申请号：US13425345

申请日：2012-03-20

申请人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Yasuyuki Sonoda

发明人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Yasuyuki Sonoda

IPC分类号： H01L29/82 ,  G11C11/02

CPC分类号： H01L27/222 ,  H01L43/08

摘要： According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.

摘要翻译： 根据一个实施例，半导体存储器件包括多个磁阻元件。 在半导体存储器件中，每个磁阻元件包括：形成在半导体衬底上的第一磁性层，第一磁性层具有垂直于其膜表面的易磁化磁化轴; 形成在所述第一磁性层上的非磁性层; 形成在所述非磁性层上的第二磁性层，所述第二磁性层具有与其膜表面垂直的容易的磁化轴; 以及侧壁膜，其被设置成覆盖每个所述磁阻元件的侧壁，并且所述侧壁膜之间具有保护膜，所述侧壁膜沿易磁化轴向所述磁阻元件提供拉伸应力。

公开(公告)号：US20130001716A1

公开(公告)日：2013-01-03

申请号：US13425309

申请日：2012-03-20

申请人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Tadashi Kai

发明人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Tadashi Kai

IPC分类号： H01L29/82 ,  H01L43/12

CPC分类号： H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.

摘要翻译： 根据实施例，磁阻元件包括下电极，下电极上的第一磁性层，第一磁性层上的第一扩散防止层，第一金属层上的第一界面磁性层，第一金属层上的非磁性层 第一界面磁性层，非磁性层上的第二界面磁性层，第二界面磁性层上的第二扩散防止层，第二扩散防止层上的第二磁性层和第二磁性层上的上部电极层。 第二界面磁性层中的晶体取向部分与另一部分的比例高于第一界面磁性层中晶体取向部分与其它部分的比例。

公开(公告)号：US20120326252A1

公开(公告)日：2012-12-27

申请号：US13425345

申请日：2012-03-20

申请人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Yasuyuki Sonoda

发明人： Koji Yamakawa ,  Katsuaki Natori ,  Daisuke Ikeno ,  Yasuyuki Sonoda

IPC分类号： H01L29/82

CPC分类号： H01L27/222 ,  H01L43/08

摘要： According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.

摘要翻译： 根据一个实施例，半导体存储器件包括多个磁阻元件。 在半导体存储器件中，每个磁阻元件包括：形成在半导体衬底上的第一磁性层，第一磁性层具有垂直于其膜表面的易磁化磁化轴; 形成在所述第一磁性层上的非磁性层; 形成在所述非磁性层上的第二磁性层，所述第二磁性层具有与其膜表面垂直的容易的磁化轴; 以及侧壁膜，其被设置成覆盖每个所述磁阻元件的侧壁，并且所述侧壁膜之间具有保护膜，所述侧壁膜沿易磁化轴向所述磁阻元件提供拉伸应力。

公开(公告)号：US20120112263A1

公开(公告)日：2012-05-10

申请号：US13351965

申请日：2012-01-17

申请人： Masayuki Tanaka ,  Daikuse Nishida ,  Ryota Fujitsuka ,  Katsuyuki Sekine ,  Akihito Yamamoto ,  Katsuaki Natori ,  Yoshio Ozawa

发明人： Masayuki Tanaka ,  Daikuse Nishida ,  Ryota Fujitsuka ,  Katsuyuki Sekine ,  Akihito Yamamoto ,  Katsuaki Natori ,  Yoshio Ozawa

IPC分类号： H01L29/788

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7883

摘要： A semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, the second insulating film including a lower silicon nitride film, a lower silicon oxide film formed on the lower silicon nitride film, an intermediate insulating film formed on the lower silicon oxide film and containing a metal element, the intermediate insulating film having a relative dielectric constant of greater than 7, an upper silicon oxide film formed on the intermediate insulating film, and an upper silicon nitride film formed on the upper silicon oxide film.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储层，形成在电荷存储层上的第二绝缘膜，以及形成在第二绝缘膜上的控制电极 ，所述第二绝缘膜包括下氮化硅膜，形成在所述下氮化硅膜上的下氧化硅膜，形成在所述下氧化硅膜上并含有金属元素的中间绝缘膜，所述中间绝缘膜具有相对电介质 大于7的常数，形成在中间绝缘膜上的上部氧化硅膜和形成在上部氧化硅膜上的上部氮化硅膜。

公开(公告)号：US20100213534A1

公开(公告)日：2010-08-26

申请号：US12709154

申请日：2010-02-19

申请人： Katsuyuki SEKINE ,  Katsuaki Natori ,  Tetsuya Kai ,  Yoshio Ozawa

发明人： Katsuyuki SEKINE ,  Katsuaki Natori ,  Tetsuya Kai ,  Yoshio Ozawa

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L29/40114 ,  H01L29/42336

摘要： In a nonvolatile semiconductor memory device provided with memory cell transistors, each of the memory cell transistors has a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and element isolation insulating films respectively. The floating gate electrode on the tunnel insulating film is provided with a first floating gate electrode and a second floating gate electrode formed sequentially from the bottom, the second floating gate electrode being narrower in a channel-width direction than the first one. Levels of upper surfaces of the element isolation insulating films and the first floating gate electrode are the same. The inter-electrode insulating film continuously covers the upper and side surfaces of the floating gate electrode and the upper surfaces of the element isolation insulating films, and is higher in a nitrogen concentration in a boundary portion to the floating gate electrode than in boundary portions to the element isolation insulating films.

摘要翻译： 在设置有存储单元晶体管的非易失性半导体存储器件中，每个存储单元晶体管分别具有隧道绝缘膜，浮栅电极，电极间绝缘膜和元件隔离绝缘膜。 隧道绝缘膜上的浮栅电极设置有从底部顺序形成的第一浮栅电极和第二浮栅电极，第二浮栅电极在沟道宽度方向比第一浮栅电极和第一浮栅电极窄。 元件隔离绝缘膜和第一浮栅电极的上表面的电平相同。 电极间绝缘膜连续地覆盖浮置栅电极的上表面和元件隔离绝缘膜的上表面，并且在与栅极电极的边界部分的氮浓度相比高于边界部分 元件隔离绝缘膜。