公开(公告)号：US20070138574A1

公开(公告)日：2007-06-21

申请号：US11563500

申请日：2006-11-27

申请人： Katsumi EIKYU ,  Tomohiro Yamashita ,  Katsuyuki Horita ,  Takashi Hayashi

发明人： Katsumi EIKYU ,  Tomohiro Yamashita ,  Katsuyuki Horita ,  Takashi Hayashi

IPC分类号： H01L29/76

CPC分类号： H01L21/823443 ,  H01L21/28114 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823835 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

摘要： The top ends of polysilicon gate electrodes with different gate lengths are formed so as to be equally high and lower than the top end of the side wall. A metal film is formed so as to cover the polysilicon gate electrodes, followed by silicidation by thermal treatment. Since the top ends of the polysilicon gate electrodes are formed lower than the top end of the side wall, a silicon side reaction is not accelerated even in the case of a fine gate length, and proceeds in a one-dimensional manner. As a result, full-silicide gate electrodes having a uniform metal composition ratio can be stably formed even using the polysilicon gates with different gate lengths.

摘要翻译： 具有不同栅极长度的多晶硅栅电极的顶端形成为等于高于侧壁的顶端的高度。 形成金属膜以覆盖多晶硅栅电极，然后通过热处理进行硅化。 由于多晶硅栅电极的顶端形成为低于侧壁的顶端，因此即使在精细栅极长度的情况下，硅侧反应也不会加速，并且以一维方式进行。 结果，即使使用具有不同栅极长度的多晶硅栅极，也可以稳定地形成具有均匀金属组成比的全硅化物栅电极。