公开(公告)号：US20090140787A1

公开(公告)日：2009-06-04

申请号：US11791801

申请日：2007-02-01

申请人： Satoru Shiratsuchi ,  Kazuhiro Fujinuma ,  Kazuhiro Fujinuma ,  Kazuhiko Yamaguchi

发明人： Satoru Shiratsuchi ,  Kazuhiro Fujinuma ,  Kazuhiro Fujinuma ,  Kazuhiko Yamaguchi

IPC分类号： H03H11/16

CPC分类号： H04L27/0014 ,  H04L27/364 ,  H04L2027/0016 ,  H04L2027/0018 ,  H04L2027/0044 ,  H04L2027/0053 ,  H04L2027/0055 ,  H04L2027/0067

摘要： A quadrature modulator divides a first signal input as a local signal into an I channel signal and a Q channel signal orthogonal to each other and outputs a second signal having a desired phase delay corresponding to direct current voltages as for the first signal by giving the direct current voltages Vi and Vq to the I channel signal and the Q channel signal, respectively. A phase comparison unit detects a phase difference θ between the first signal and the second signal. A setting unit sets the desired phase delay. A controller section controls the direct current voltages supplied to the I channel signal and the Q channel signal respectively in the quadrature modulator so that an output value corresponding to the phase difference θ detected by the phase comparison unit is equal to a value corresponding to the desired phase delay set by the setting unit, and controls the direct current voltages to be the direct current voltages Vi and Vq satisfying the relation of Vi=cos θ and Vq=sin θ.

摘要翻译： 正交调制器将作为本地信号输入的第一信号划分成彼此正交的I信道信号和Q信道信号，并通过给出直接的方式输出具有与直流电压相对应的期望相位延迟的第二信号 电流电压Vi和Vq分别分配给I通道信号和Q通道信号。 相位比较单元检测第一信号和第二信号之间的相位差θ。 设置单元设置所需的相位延迟。 控制器部分控制正交调制器中分别提供给I通道信号和Q通道信号的直流电压，使得与由相位比较单元检测的相位差θ相对应的输出值等于对应于期望值的值 相位延迟，并且将直流电压控制为满足Vi =cosθ和Vq =sinθ的关系的直流电压Vi和Vq。

公开(公告)号：US08143926B2

公开(公告)日：2012-03-27

申请号：US12899925

申请日：2010-10-07

申请人： Kazuhiko Yamaguchi ,  Kazuhiro Fujinuma

发明人： Kazuhiko Yamaguchi ,  Kazuhiro Fujinuma

IPC分类号： H04L7/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H03L7/0812

摘要： It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. In the data signal generating apparatus according to the present invention, synchronization means 25 for synchronizing a data output unit 11 with a multiplexer 13 has a phase comparator 16 for comparing the phase of a data synchronization clock signal outputted from a data output unit 11 in synchronization with the timing to update parallel data, with the phase of a divided clock signal A produced by dividing the frequency of a reference clock signal CK1 by a plural number “m” in the multiplexer 13, the signal A being used for determining the timing to performing parallel-serial conversion, a variable delay device 30 for adding a desired delay to a data request signal A′, the variable delay device 30 being constituted by an orthogonal modulation type delay device, and a control unit 26 for controlling a direct control signal to be inputted into the variable delay device 30 on the basis of a comparing result obtained from the phase comparator 16 to synchronize the timing to have the data output unit 11 update the parallel data with the timing to have the multiplexer 13 perform parallel-serial conversion processing.

摘要翻译： 本发明的目的是提供一种尺寸小的数据信号发生装置，并且可以以期望的顺序输出串行数据，而不会产生不确定的状态以及能够处理抖动测量。 在根据本发明的数据信号发生装置中，用于使数据输出单元11与多路复用器13同步的同步装置25具有相位比较器16，用于将从数据输出单元11输出的数据同步时钟信号的相位同步 具有更新并行数据的定时，通过在多路复用器13中将参考时钟信号CK1的频率除以多个“m”而产生的分频时钟信号A的相位，信号A用于确定定时 执行并行串行转换，可变延迟装置30，用于将数据请求信号A'加上期望的延迟，可变延迟装置30由正交调制型延迟装置构成，控制单元26用于控制直接控制信号 基于从相位比较器16获得的比较结果输入到可变延迟装置30中，以使具有t的定时同步 数据输出单元11用多路复用器13执行并行串行转换处理的定时更新并行数据。

公开(公告)号：US20110026573A1

公开(公告)日：2011-02-03

申请号：US12899925

申请日：2010-10-07

申请人： Kazuhiko Yamaguchi ,  Kazuhiro Fujinuma

发明人： Kazuhiko Yamaguchi ,  Kazuhiro Fujinuma

IPC分类号： H04B17/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H03L7/0812

摘要： It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. In the data signal generating apparatus according to the present invention, synchronization means 25 for synchronizing a data output unit 11 with a multiplexer 13 has a phase comparator 16 for comparing the phase of a data synchronization clock signal outputted from a data output unit 11 in synchronization with the timing to update parallel data, with the phase of a divided clock signal A produced by dividing the frequency of a reference clock signal CK1 by a plural number “m” in the multiplexer 13, the signal A being used for determining the timing to performing parallel-serial conversion, a variable delay device 30 for adding a desired delay to a data request signal A′, the variable delay device 30 being constituted by an orthogonal modulation type delay device, and a control unit 26 for controlling a direct control signal to be inputted into the variable delay device 30 on the basis of a comparing result obtained from the phase comparator 16 to synchronize the timing to have the data output unit 11 update the parallel data with the timing to have the multiplexer 13 perform parallel-serial conversion processing.

摘要翻译： 本发明的目的是提供一种尺寸小的数据信号发生装置，并且可以以期望的顺序输出串行数据，而不会产生不确定的状态以及能够处理抖动测量。 在根据本发明的数据信号发生装置中，用于使数据输出单元11与多路复用器13同步的同步装置25具有相位比较器16，用于将从数据输出单元11输出的数据同步时钟信号的相位同步 具有更新并行数据的定时，通过在多路复用器13中将参考时钟信号CK1的频率除以多个“m”而产生的分频时钟信号A的相位，信号A用于确定定时 执行并行串行转换，可变延迟装置30，用于将数据请求信号A'加上期望的延迟，可变延迟装置30由正交调制型延迟装置构成，控制单元26用于控制直接控制信号 基于从相位比较器16获得的比较结果输入到可变延迟装置30中，以使具有t的定时同步 数据输出单元11用多路复用器13执行并行串行转换处理的定时更新并行数据。

公开(公告)号：US07671691B2

公开(公告)日：2010-03-02

申请号：US11791801

申请日：2007-02-01

申请人： Satoru Shiratsuchi ,  Kazuhiro Fujinuma ,  Kazuhiko Yamaguchi

发明人： Satoru Shiratsuchi ,  Kazuhiro Fujinuma ,  Kazuhiko Yamaguchi

IPC分类号： H03C3/00

CPC分类号： H04L27/0014 ,  H04L27/364 ,  H04L2027/0016 ,  H04L2027/0018 ,  H04L2027/0044 ,  H04L2027/0053 ,  H04L2027/0055 ,  H04L2027/0067

摘要： A quadrature modulator divides a first signal input as a local signal into an I channel signal and a Q channel signal orthogonal to each other and outputs a second signal having a desired phase delay corresponding to direct current voltages as for the first signal by giving the direct current voltages Vi and Vq to the I channel signal and the Q channel signal, respectively. A phase comparison unit detects a phase difference θ between the first signal and the second signal. A setting unit sets the desired phase delay. A controller section controls the direct current voltages supplied to the I channel signal and the Q channel signal respectively in the quadrature modulator so that an output value corresponding to the phase difference θ detected by the phase comparison unit is equal to a value corresponding to the desired phase delay set by the setting unit, and controls the direct current voltages to be the direct current voltages Vi and Vq satisfying the relation of Vi=cos θ and Vq=sin θ.

摘要翻译： 正交调制器将作为本地信号输入的第一信号划分成彼此正交的I信道信号和Q信道信号，并通过给出直接的方式输出具有与直流电压相对应的期望相位延迟的第二信号 电流电压Vi和Vq分别分配给I通道信号和Q通道信号。 相位比较单元检测相位差; 在第一信号和第二信号之间。 设置单元设置所需的相位延迟。 控制器部分控制正交调制器中分别提供给I通道信号和Q通道信号的直流电压，使得对应于相位差的输出值; 由相位比较单元检测的等于与设定单元设定的期望相位延迟对应的值，将直流电压控制为满足Vi = cos＆amp; t s的关系的直流电压Vi，Vq; Vq = sin＆thetas;

公开(公告)号：US20090243680A1

公开(公告)日：2009-10-01

申请号：US12295208

申请日：2007-03-26

申请人： Kazuhiko Yamaguchi ,  Kazuhiro Fujinuma

发明人： Kazuhiko Yamaguchi ,  Kazuhiro Fujinuma

IPC分类号： H03L7/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H03L7/0812

摘要： It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. In the data signal generating apparatus according to the present invention, synchronization means 25 for synchronizing a data output unit 11 with a multiplexer 13 has a phase comparator 16 for comparing the phase of a data synchronization clock signal outputted from a data output unit 11 in synchronization with the timing to update parallel data, with the phase of a divided clock signal A produced by dividing the frequency of a reference clock signal CK1 by a plural number “m” in the multiplexer 13, the signal A being used for determining the timing to performing parallel-serial conversion, a variable delay device 30 for adding a desired delay to a data request signal A′, the variable delay device 30 being constituted by an orthogonal modulation type delay device, and a control unit 26 for controlling a direct control signal to be inputted into the variable delay device 30 on the basis of a comparing result obtained from the phase comparator 16 to synchronize the timing to have the data output unit 11 update the parallel data with the timing to have the multiplexer 13 perform parallel-serial conversion processing.

摘要翻译： 本发明的目的是提供一种尺寸小的数据信号发生装置，并且可以以期望的顺序输出串行数据，而不会产生不确定的状态以及能够处理抖动测量。 在根据本发明的数据信号发生装置中，用于使数据输出单元11与多路复用器13同步的同步装置25具有相位比较器16，用于将从数据输出单元11输出的数据同步时钟信号的相位同步 具有更新并行数据的定时，通过在多路复用器13中将参考时钟信号CK1的频率除以多个“m”而产生的分频时钟信号A的相位，信号A用于确定定时 执行并行串行转换，可变延迟装置30，用于将数据请求信号A'加上期望的延迟，可变延迟装置30由正交调制型延迟装置构成，控制单元26用于控制直接控制信号 基于从相位比较器16获得的比较结果输入到可变延迟装置30中，以使定时同步以具有数据 输出单元11利用具有多路复用器13执行并行 - 串行转换处理的定时更新并行数据。

公开(公告)号：US07893740B2

公开(公告)日：2011-02-22

申请号：US12295208

申请日：2007-03-26

申请人： Kazuhiko Yamaguchi ,  Kazuhiro Fujinuma

发明人： Kazuhiko Yamaguchi ,  Kazuhiro Fujinuma

IPC分类号： H04L7/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H03L7/0812

摘要： A data signal generating apparatus with a data output unit for outputting m-bit parallel data and a data synchronization clock signal synchronized with the parallel data in response to a data request signal produced by dividing the frequency of a reference clock signal by “m.” An m:1 multiplexer for receiving the parallel data in response to a latch signal produced by dividing the frequency of the reference clock signal by “m,” and outputting, at a rate of the reference clock signal, data synchronization serial data. Synchronization means for comparing the phases of the data synchronization clock signal and the latch signal, for synchronizing the parallel data with the latch signal, and for producing a control signal, and which delays, on the basis of the control signal, the reference clock signal or a divided clock signal (dividing the frequency of the reference clock signal by “m” or less).

摘要翻译： 一种数据信号发生装置，具有数据输出单元，用于响应于通过将参考时钟信号的频率除以“m”而产生的数据请求信号，输出m位并行数据和与并行数据同步的数据同步时钟信号。 一种m：1多路复用器，用于响应于通过将参考时钟信号的频率除以“m”而产生的锁存信号，并以基准时钟信号的速率输出数据同步串行数据来接收并行数据。 同步装置，用于比较数据同步时钟信号和锁存信号的相位，用于使并行数据与锁存信号同步，并产生控制信号，并且基于控制信号延迟基准时钟信号 或分频时钟信号（将参考时钟信号的频率除以“m”或更小）。

公开(公告)号：US08005180B2

公开(公告)日：2011-08-23

申请号：US12294404

申请日：2007-03-26

申请人： Kazuhiro Fujinuma ,  Kazuhiro Yamane

发明人： Kazuhiro Fujinuma ,  Kazuhiro Yamane

IPC分类号： H04L25/00

CPC分类号： H04L7/0337 ,  H04L25/03828

摘要： The object of the present invention is to provide a data decision apparatus and an error measurement apparatus which can set the phase of the clock to the optimum state with respect to the data signal without continuously sweeping of the phase, and can keep the state for a long time. The data decision apparatus according to the present invention comprises a delay device (34) for delaying a data signal (Dc) outputted from a decision device (31) by one bit, a first phase detector (35) for detecting a phase difference between a data signal (Db) to be inputted to the decision device (31) and the data signal (Dc) outputted from the decision device (31), a second phase detector (36) for detecting a phase difference between the data signal (Dc) outputted from the decision device (31) and a data signal (Dd) outputted from the delay device (34), a third phase detector (37) for outputting a base voltage with respect to the output values of the first and second phase detectors (35 and 36), and a phase controller (38) for controlling a phase shift amount of a variable delay device (32) to equalize an output value (P1) of the first phase detector (35) to a center value between an output value (P2) of the second phase detector (36) and the base voltage (P3).

摘要翻译： 本发明的目的是提供一种数据判定装置和误差测量装置，其可以将相位相对于数据信号的时钟相位设置为相位的最佳状态，而不会持续扫描相位，并且可以保持状态 长时间。 根据本发明的数据判定装置包括延迟装置（34），用于将从判定装置（31）输出的数据信号（Dc）延迟一位，第一相位检测器（35） 输入到判定装置（31）的数据信号（Db）和从判定装置（31）输出的数据信号（Dc）;第二相位检测器（36），用于检测数据信号（Dc） 从所述判定装置（31）输出的数据信号（Dd）和从所述延迟装置（34）输出的数据信号（Dd）;第三相位检测器（37），用于相对于所述第一和第二相位检测器的输出值输出基极电压 35和36）和相位控制器（38），用于控制可变延迟装置（32）的相移量以将第一相位检测器（35）的输出值（P1）均衡到输出值 （P2）和基极电压（P3）。

公开(公告)号：US08005134B2

公开(公告)日：2011-08-23

申请号：US12295227

申请日：2007-03-26

申请人： Kazuhiro Yamane ,  Kazuhiro Fujinuma

发明人： Kazuhiro Yamane ,  Kazuhiro Fujinuma

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H03K5/26 ,  H03K5/08 ,  H03K5/24

摘要： The object of the present invention is to provide a waveform shaping device and an error measurement device which can perform a waveform shaping operation with the sufficient amplitude margin, even if the mark ratio of the inputted data signal is significantly varied and the amplitude of the inputted data signal is decreased. The waveform shaping device according to the present invention comprises a voltage detector (22) for detecting an inputted data signal (Da) to obtain an amplitude value and the center amplitude voltage of the inputted data signal (Da), a reference voltage generator (23) for generate the reference voltage corresponding to the center amplitude voltage, and a comparator (25) for comparing the inputted data signal (Da) with the reference voltage, and in which the waveform shaping device further comprises a correction information outputting section (27) for outputting correction information V on the basis of a mark ratio (M) and an amplitude of the inputted data signal (Da), the correction information V used to correct the center amplitude voltage detected by the voltage detector (22), and a correction section (28) correct the reference voltage or the inputted data signal to be inputted to the comparator (25) on the basis of the correction information (V).

摘要翻译： 本发明的目的是提供一种能够以足够的幅度进行波形整形的波形整形装置和误差测量装置，即使输入的数据信号的标记比显着变化，输入的幅度 数据信号减少。 根据本发明的波形整形装置包括用于检测输入数据信号（Da）以获得输入数据信号（Da）的振幅值和中心振幅电压的电压检测器（22），参考电压发生器（23） ），用于产生与中心振幅电压相对应的参考电压;以及比较器（25），用于将输入的数据信号（Da）与参考电压进行比较，其中波形整形装置还包括校正信息输出部分（27） 用于根据标记比（M）和输入数据信号（Da）的幅度输出校正信息V，用于校正由电压检测器（22）检测的中心振幅电压的校正信息V，以及校正 部分（28）基于校正信息（V）来校正要输入到比较器（25）的参考电压或输入的数据信号。

公开(公告)号：US20090279595A1

公开(公告)日：2009-11-12

申请号：US12295227

申请日：2007-03-26

申请人： Kazuhiro Yamane ,  Kazuhiro Fujinuma

发明人： Kazuhiro Yamane ,  Kazuhiro Fujinuma

IPC分类号： H04B17/00

CPC分类号： H03K5/26 ,  H03K5/08 ,  H03K5/24

摘要： The object of the present invention is to provide a waveform shaping device and an error measurement device which can perform a waveform shaping operation with the sufficient amplitude margin, even if the mark ratio of the inputted data signal is significantly varied and the amplitude of the inputted data signal is decreased. The waveform shaping device according to the present invention comprises a voltage detector (22) for detecting an inputted data signal (Da) to obtain an amplitude value and the center amplitude voltage of the inputted data signal (Da), a reference voltage generator (23) for generate the reference voltage corresponding to the center amplitude voltage, and a comparator (25) for comparing the inputted data signal (Da) with the reference voltage, and in which the waveform shaping device further comprises a correction information outputting section (27) for outputting correction information V on the basis of a mark ratio (M) and an amplitude of the inputted data signal (Da), the correction information V used to correct the center amplitude voltage detected by the voltage detector (22), and a correction section (28) correct the reference voltage or the inputted data signal to be inputted to the comparator (25) on the basis of the correction information (V).

摘要翻译： 本发明的目的是提供一种能够以足够的幅度进行波形整形的波形整形装置和误差测量装置，即使输入的数据信号的标记比显着变化，输入的幅度 数据信号减少。 根据本发明的波形整形装置包括用于检测输入数据信号（Da）以获得输入数据信号（Da）的振幅值和中心振幅电压的电压检测器（22），参考电压发生器（23） ），用于产生与中心振幅电压相对应的参考电压;以及比较器（25），用于将输入的数据信号（Da）与参考电压进行比较，其中波形整形装置还包括校正信息输出部分（27） 用于输出校正信息 V，校正信息 V用于 校正由电压检测器（22）检测到的中心振幅电压，校正部件（28）根据校正信息（ V）。

公开(公告)号：US20090252270A1

公开(公告)日：2009-10-08

申请号：US12294404

申请日：2007-03-26

申请人： Kazuhiro Fujinuma ,  Kazuhiro Yamane

发明人： Kazuhiro Fujinuma ,  Kazuhiro Yamane

IPC分类号： H04L7/00

CPC分类号： H04L7/0337 ,  H04L25/03828

摘要： The object of the present invention is to provide a data decision apparatus and an error measurement apparatus which can set the phase of the clock to the optimum state with respect to the data signal without continuously sweeping of the phase, and can keep the state for a long time. The data decision apparatus according to the present invention comprises a delay device (34) for delaying a data signal (Dc) outputted from a decision device (31) by one bit, a first phase detector (35) for detecting a phase difference between a data signal (Db) to be inputted to the decision device (31) and the data signal (Dc) outputted from the decision device (31), a second phase detector (36) for detecting a phase difference between the data signal (Dc) outputted from the decision device (31) and a data signal (Dd) outputted from the delay device (34), a third phase detector (37) for outputting a base voltage with respect to the output values of the first and second phase detectors (35 and 36), and a phase controller (38) for controlling a phase shift amount of a variable delay device (32) to equalize an output value (P1) of the first phase detector (35) to a center value between an output value (P2) of the second phase detector (36) and the base voltage (P3).

摘要翻译： 本发明的目的是提供一种数据判定装置和误差测量装置，其可以将相位相对于数据信号的时钟相位设置为相位的最佳状态，而不会持续扫描相位，并且可以保持状态 长时间。 根据本发明的数据判定装置包括延迟装置（34），用于将从判定装置（31）输出的数据信号（Dc）延迟一位，第一相位检测器（35） 输入到判定装置（31）的数据信号（Db）和从判定装置（31）输出的数据信号（Dc）;第二相位检测器（36），用于检测数据信号（Dc） 从所述判定装置（31）输出的数据信号（Dd）和从所述延迟装置（34）输出的数据信号（Dd）;第三相位检测器（37），用于相对于所述第一和第二相位检测器的输出值输出基极电压 35和36）和相位控制器（38），用于控制可变延迟装置（32）的相移量以将第一相位检测器（35）的输出值（P1）均衡到输出值 （P2）和基极电压（P3）。