利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

71 条记录 (耗时 0.028 秒)

    Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs
    8.
    发明授权
    Method of manufacturing a semiconductor device having non-volatile memory cell portion with single transistor type memory cells and peripheral portion with MISFETs 失效
    具有具有单晶体管型存储单元的非易失性存储单元部分和具有MISFET的周边部分的半导体器件的制造方法

    公开(公告)号：US06451643B2

    公开(公告)日：2002-09-17

    申请号：US09873451

    申请日：2001-06-05

    申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    IPC分类号： H01L218238

    CPC分类号： H01L27/105 ,  G11C16/0416 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886

    摘要： A method of manufacturing a semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions. By this method, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. The first semiconductor region is formed to have a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Carriers stored in the floating gate electrode are transferred between the floating gate electrode and the first semiconductor region by tunneling through the insulating film beneath the floating gate electrode. The method further features the formation of MISFETs of peripheral circuits.

    摘要翻译： 一种制造具有非易失性存储单元的半导体存储器件的方法，每个半导体存储器单元均由具有浮置栅极和控制栅极以及第一和第二半导体区域的MISFET构成。 通过该方法，引入杂质（例如砷）以形成第一和第二半导体区域，但是，在第二半导体区域的形成中引入较低剂量的砷。 第一半导体区域形成为具有大于第二半导体区域的结深度的结深度，并且第一和第二半导体区域都具有在浮栅电极下延伸的部分。 存储在浮置栅电极中的载体通过隧穿穿过浮栅电极下方的绝缘膜而在浮置栅极电极和第一半导体区域之间传输。 该方法还特征在于外围电路的MISFET的形成。

    Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells
    9.
    发明授权
    Method of manufacturing a semiconductor IC device having single transistor type nonvolatile memory cells 失效
    具有单晶体管型非易失性存储单元的半导体IC器件的制造方法

    公开(公告)号：US5904518A

    公开(公告)日：1999-05-18

    申请号：US885184

    申请日：1997-06-30

    申请人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    发明人： Kazuhiro Komori ,  Toshiaki Nishimoto ,  Satoshi Meguro ,  Hitoshi Kume ,  Yoshiaki Kamigaki

    IPC分类号： H01L21/8247 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7885 ,  H01L29/7886 ,  G11C16/0416 ,  H01L27/0688

    摘要： A method of manufacturing a semiconductor memory device having nonvolatile memory cells of a single-element type. The method provides for the formation of a floating gate electrode insulatedly on a main surface of a semiconductor substrate and a control gate electrode on the floating gate via a second gate insulating film. Also by this method, an impurity, for example, arsenic, is introduced in self-alignment with the pair of opposing end sides of the control gate electrode to form both the first and second semiconductor regions but, however, a lower dose of arsenic is introduced in the formation of the second semiconductor region. In accordance with the scheme, the first semiconductor region is formed to have a junction depth greater than the junction depth associated with the second semiconductor region and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. Moreover, carriers which are stored in the floating gate electrode are transferred therefrom to the first semiconductor region, for example, during an erase operation of the memory, by tunneling through the insulating film beneath the floating gate electrode. The method also calls for the formation of MISFETs associated with peripheral circuitry of the memory.

    摘要翻译： 一种制造具有单一元件类型的非易失性存储单元的半导体存储器件的方法。 该方法提供了通过第二栅极绝缘膜在浮栅上隔离地形成半导体衬底的主表面上的浮栅电极和控制栅电极。 此外，通过该方法，与控制栅电极的一对相对端侧自对准地引入杂质，例如砷，以形成第一和第二半导体区域，但是较低剂量的砷为 引入第二半导体区域的形成。 根据该方案，第一半导体区域形成为具有大于与第二半导体区域相关联的结深度的结深度，并且第一和第二半导体区域都具有在浮置栅极下方延伸的部分。 此外，例如在存储器的擦除操作期间，存储在浮置栅电极中的载流子通过隧穿穿过浮置栅电极下方的绝缘膜而被转移到第一半导体区域。 该方法还要求形成与存储器的外围电路相关联的MISFET。