Optical bus system and signal processor

    公开(公告)号:US06634812B2

    公开(公告)日:2003-10-21

    申请号:US09941675

    申请日:2001-08-30

    IPC分类号: H04B1010

    CPC分类号: H04B10/801 H05K1/02 H05K1/14

    摘要: An optical bus system comprising an optical bus is furnished, along two opposed edges, with a plurality of signal light input/output portions for inputting and outputting signal light to and from the bus. Any one of the signal light input/output portions on one edge of the bus inputs signal light thereto and propagates the light to the opposite edge at which another signal light input/output portion outputs the propagated signal light from the bus. The system also comprises a plurality of light emitting/receiving circuits corresponding to the signal light input/output portions. Each light emitting/receiving circuit has a signal light sending unit and a signal light receiving unit. The signal light sending unit generates signal light and sends the generated signal light into the optical bus through the corresponding signal light input/output portion. The signal light receiving unit acquires a received light signal upon receipt of the signal light output by the corresponding signal light input/output portion. At least one of the light receiving/emitting circuits on each edge of the optical bus has a repeating or reflecting part that causes the corresponding signal light sending unit to send out the signal light received by the corresponding signal light receiving unit.

    Optical bus system and signal processor
    3.
    发明授权
    Optical bus system and signal processor 失效
    光总线系统和信号处理器

    公开(公告)号:US06317242B1

    公开(公告)日:2001-11-13

    申请号:US09221994

    申请日:1998-12-29

    IPC分类号: H04B1017

    CPC分类号: H04B10/801 H05K1/02 H05K1/14

    摘要: An optical bus system comprising an optical bus is furnished, along two opposed edges, with a plurality of signal light input/output portions for inputting and outputting signal light to and from the bus. Any one of the signal light input/output portions on one edge of the bus inputs signal light thereto and propagates the light to the opposite edge at which another signal light input/output portion outputs the propagated signal light from the bus. The system also comprises a plurality of light emitting/receiving circuits corresponding to the signal light input/output portions. Each light emitting/receiving circuit has a signal light sending unit and a signal light receiving unit. The signal light sending unit generates signal light and sends the generated signal light into the optical bus through the corresponding signal light input/output portion. The signal light receiving unit acquires a received light signal upon receipt of the signal light output by the corresponding signal light input/output portion. At least one of the light receiving/emitting circuits on each edge of the optical bus has a repeating or reflecting part that causes the corresponding signal light sending unit to send out the signal light received by the corresponding signal light receiving unit.

    摘要翻译: 沿着两个相对的边缘,提供包括光学总线的光学总线系统,该多个信号光输入/输出部分用于向总线输入和输出信号光。 总线输入的一个边缘上的信号光输入/输出部分中的任何一个信号发光,并将光传播到另一信号光输入/输出部分从总线输出传播信号光的相对边缘。 该系统还包括对应于信号光输入/输出部分的多个发光/接收电路。 每个发光/接收电路具有信号光发送单元和信号光接收单元。 信号光发送单元产生信号光,并通过相应的信号光输入/输出部分将产生的信号光发送到光总线。 信号光接收单元在接收到由对应的信号光输入/输出部分输出的信号光时获取接收的光信号。 光总线的每个边缘上的光接收/发射电路中的至少一个具有使相应的信号光发送单元发出由对应的信号光接收单元接收的信号光的重复或反射部分。

    Multiprocessor system
    4.
    发明授权
    Multiprocessor system 失效
    多处理器系统

    公开(公告)号:US06651139B1

    公开(公告)日:2003-11-18

    申请号:US09517624

    申请日:2000-03-03

    IPC分类号: G06F1200

    CPC分类号: G06F12/0813 G06F12/084

    摘要: The invention relates to a multiprocessor system having plural processors and an optical bus shared by the plural processors, and intends to simplify the cache control, reduce the volume of hardware, and shorten the memory access processing time. For this purpose, the multiprocessor system of the invention includes a shared memory, a cache memory connected to the shared memory, an optical bus connected to the cache memory, and plural processors connected to the optical bus, which access to the cache memory through the optical bus.

    摘要翻译: 本发明涉及具有多个处理器和由多个处理器共享的光总线的多处理器系统,并且旨在简化高速缓存控制,减少硬件量并缩短存储器访问处理时间。 为此,本发明的多处理器系统包括共享存储器,连接到共享存储器的高速缓冲存储器,连接到高速缓冲存储器的光总线,以及连接到光总线的多个处理器,其通过该存储器访问高速缓冲存储器 光学总线。

    Communication device, multiple bus control device and LSI for controlling multiple bus
    6.
    发明授权
    Communication device, multiple bus control device and LSI for controlling multiple bus 失效
    通信装置,多总线控制装置和LSI用于控制多个总线

    公开(公告)号:US06493784B1

    公开(公告)日:2002-12-10

    申请号:US09454858

    申请日:1999-12-07

    IPC分类号: G06F1200

    CPC分类号: G06F13/362 G06F13/1652

    摘要: The present invention provides a multiple bus control device and others which can also be applied to access control by a signal having a directional propagation property for implementing various communication between/among modules. Each of plural modules makes a request for communication to a multiple bus control device by sending communication request information for specifying one or more communication partner modules to the multiple bus control device. The multiple bus control device checks an idle state of a module to be communicated and an idle channel in a multiple bus based upon received communication request information and permits communication between a module which sends communication request information using the idle channel and a communication partner module specified in the communication request information.

    摘要翻译: 本发明提供一种多总线控制装置等,其也可以应用于具有用于实现模块之间/之间的各种通信的具有定向传播特性的信号的访问控制。 多个模块中的每一个通过向多总线控制装置发送用于指定一个或多个通信伙伴模块的通信请求信息来向多总线控制装置发出通信请求。 多总线控制装置基于所接收的通信请求信息来检查要传送的模块的空闲状态和多总线中的空闲信道,并允许使用空闲信道发送通信请求信息的模块与指定的通信伙伴模块之间的通信 在通信请求信息中。