公开(公告)号：US20080276112A1

公开(公告)日：2008-11-06

申请号：US12169853

申请日：2008-07-09

申请人： SHIGEZUMI MATSUI ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

发明人： SHIGEZUMI MATSUI ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

IPC分类号： H04L7/00

CPC分类号： G06F13/4243 ,  G06F13/1689

摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

公开(公告)号：US07412616B2

公开(公告)日：2008-08-12

申请号：US10895394

申请日：2004-07-21

申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

IPC分类号： H04L7/00

CPC分类号： G06F13/4243 ,  G06F13/1689

摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

公开(公告)号：US07324225B2

公开(公告)日：2008-01-29

申请号：US09865570

申请日：2001-05-29

申请人： Shinobu Ozeki ,  Tsutomu Hamada ,  Junji Okada ,  Masao Funada ,  Takeshi Kamimura ,  Hidenori Yamada ,  Kazuhiro Sakai ,  Shinya Kyozuka ,  Hiroki Ishida ,  Osamu Takanashi ,  Masaaki Miura ,  Kenichi Kobayashi ,  Tsuyoshi Yaguchi ,  Kazuhiro Hama ,  Toshiki Matsui ,  Yasuhiro Arai ,  Hirotaka Mori

发明人： Shinobu Ozeki ,  Tsutomu Hamada ,  Junji Okada ,  Masao Funada ,  Takeshi Kamimura ,  Hidenori Yamada ,  Kazuhiro Sakai ,  Shinya Kyozuka ,  Hiroki Ishida ,  Osamu Takanashi ,  Masaaki Miura ,  Kenichi Kobayashi ,  Tsuyoshi Yaguchi ,  Kazuhiro Hama ,  Toshiki Matsui ,  Yasuhiro Arai ,  Hirotaka Mori

IPC分类号： B41J1/00 ,  G06K1/00 ,  B41B1/00 ,  G06F15/00 ,  B41F1/00

CPC分类号： H04N1/0083 ,  H04N1/00

摘要： A multifunction system has advanced functions and high speed capability and is excellent in expandability. The multifunction system includes a controller, an IIT, an IOT, and a light distributing device. For a print job, print data outputted from the controller is converted into optical signals, which enter a light distributing device and are transmitted to the IOT of the emission side. The IOT prints the received data onto a printer. For a copy job, copy data outputted from IIT is converted into optical signals, which enter the light distributing device, and are transmitted to the IOT of the emission side. For a scan job, scan data outputted from the scanner is converted into optical signals, which enter the light distributing device, and are transmitted to the controller of the emission side. The controller processes the received data.

摘要翻译： 多功能系统具有先进的功能和高速能力，并且具有优异的可扩展性。 多功能系统包括控制器，IIT，IOT以及配光装置。 对于打印作业，从控制器输出的打印数据被转换成光信号，其进入光分配装置并被发送到发射侧的IOT。 IOT将接收到的数据打印到打印机上。 对于复印作业，从IIT输出的复制数据被转换成进入光分配装置的光信号，并被发送到发射侧的IOT。 对于扫描作业，从扫描仪输出的扫描数据被转换成进入光分配装置的光信号，并被发送到发射侧的控制器。 控制器处理接收到的数据。

公开(公告)号：US07945801B2

公开(公告)日：2011-05-17

申请号：US12169853

申请日：2008-07-09

申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

IPC分类号： H04L7/00

CPC分类号： G06F13/4243 ,  G06F13/1689

摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。

公开(公告)号：US20050047192A1

公开(公告)日：2005-03-03

申请号：US10895394

申请日：2004-07-21

申请人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

发明人： Shigezumi Matsui ,  Takashi Sato ,  Kazuyuki Sakata ,  Tsuyoshi Yaguchi ,  Kenzo Kuwabara ,  Atsushi Nakamura ,  Motoo Suwa ,  Ryoichi Sano ,  Hisashi Shiota

IPC分类号： G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G06F15/78 ,  G11C11/22 ,  G11C11/401 ,  G11C11/407

CPC分类号： G06F13/4243 ,  G06F13/1689

摘要： A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.

摘要翻译： 存储器接口电路可连接到DDR-SDRAM，其与数据选通信号一起与数据选通信号一起输出读取数据。 时钟发生器产生提供给DDR-SDRAM的内部时钟信号和存储器时钟信号。 存储器接口电路通过使用相对于DDR-SDRAM在读周期中输入的数据选通信号，相对于相应的内部时钟信号确定数据选通信号的到达延迟，基于信号对所读取的数据进行采样 通过移位到达数据选通信号的相位来获得，并且基于到达延迟的确定结果将采样的读取数据与相应的内部时钟信号同步。