公开(公告)号：US20070114614A1

公开(公告)日：2007-05-24

申请号：US11623806

申请日：2007-01-17

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/94 ,  H01L23/58

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区（28）的上表面中，在NMOS（14）和PMOS（15）之间形成有与p型杂质区（33）接触的p + p型井（29）。 电极（41）位于p + +型杂质区域（33）上，电极（41）连接到高电压侧浮置偏移电压（VS）。 p型+杂质区域（33）的杂质浓度比p型阱（29）高，比p型阱（29）浅。 在p + + / - 型杂质区域（33）和PMOS（15）之间，形成n + +型杂质区域（32）的上表面 n型杂质区（28）。 电极（40）位于n + + +型杂质区（32）上，电极（40）连接到高压侧浮动电源绝对电压（VB）。

公开(公告)号：US20060011960A1

公开(公告)日：2006-01-19

申请号：US11229724

申请日：2005-09-20

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/94

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区（28）的上表面中，在NMOS（14）和PMOS（15）之间形成有与p型杂质区（33）接触的p + p型井（29）。 电极（41）位于p + +型杂质区域（33）上，电极（41）连接到高电压侧浮置偏移电压（VS）。 p型+杂质区域（33）的杂质浓度比p型阱（29）高，比p型阱（29）浅。 在p + + / - 型杂质区域（33）和PMOS（15）之间，形成n + +型杂质区域（32）的上表面 n型杂质区（28）。 电极（40）位于n + + +型杂质区（32）上，电极（40）连接到高压侧浮动电源绝对电压（VB）。

公开(公告)号：US07190034B2

公开(公告)日：2007-03-13

申请号：US11229724

申请日：2005-09-20

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区（28）的上表面中，在NMOS（14）和PMOS（15）之间形成有与p型杂质区（33）接触的p + p型井（29）。 电极（41）位于p + +型杂质区域（33）上，电极（41）连接到高电压侧浮置偏移电压（VS）。 p型+杂质区域（33）的杂质浓度比p型阱（29）高，比p型阱（29）浅。 在p + + / - 型杂质区域（33）和PMOS（15）之间，形成n + +型杂质区域（32）的上表面 n型杂质区（28）。 电极（40）位于n + + +型杂质区（32）上，电极（40）连接到高压侧浮动电源绝对电压（VB）。

公开(公告)号：US07545005B2

公开(公告)日：2009-06-09

申请号：US12164739

申请日：2008-06-30

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区的上表​​面中，在NMOS与PMOS之间形成p +型杂质区，与p型阱接触。 电极位于p +型杂质区上，电极连接到高压侧浮置偏移电压（VS）。 p +型杂质区的杂质浓度比p型阱高，比p型阱浅。 在p +型杂质区和PMOS之间，在n型杂质区的上表​​面形成n +型杂质区。 电极位于n +型杂质区域，电极连接到高压侧浮动电源绝对电压（VB）。

公开(公告)号：US07408228B2

公开(公告)日：2008-08-05

申请号：US11623806

申请日：2007-01-17

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区（28）的上表面中，在NMOS（14）和PMOS（15）之间形成有与p型杂质区（33）接触的p + p型井（29）。 电极（41）位于p + +型杂质区域（33）上，电极（41）连接到高电压侧浮置偏移电压（VS）。 p型+杂质区域（33）的杂质浓度比p型阱（29）高，比p型阱（29）浅。 在p + + / - 型杂质区域（33）和PMOS（15）之间，形成n + +型杂质区域（32）的上表面 n型杂质区（28）。 电极（40）位于n + + +型杂质区（32）上，电极（40）连接到高压侧浮动电源绝对电压（VB）。

公开(公告)号：US07777279B2

公开(公告)日：2010-08-17

申请号：US12164696

申请日：2008-06-30

申请人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

发明人： Kazunari Hatade ,  Hajime Akiyama ,  Kazuhiro Shimizu

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L21/761 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region, a p+-type impurity region is formed between an NMOS and a PMOS and in contact with a p-type well. An electrode resides on the p+-type impurity region and the electrode is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region has a higher impurity concentration than the p-type well and is shallower than the p-type well. Between the p+-type impurity region and the PMOS, an n+-type impurity region is formed in the upper surface of the n-type impurity region. An electrode resides on the n+-type impurity region and the electrode is connected to a high-voltage-side floating supply absolute voltage (VB).

摘要翻译： 提供一种半导体器件，其能够避免由高压侧浮动偏置电压（VS）的负变化引起的故障和闭锁故障。 在n型杂质区的上表​​面中，在NMOS与PMOS之间形成p +型杂质区，与p型阱接触。 电极位于p +型杂质区上，电极连接到高压侧浮置偏移电压（VS）。 p +型杂质区的杂质浓度比p型阱高，比p型阱浅。 在p +型杂质区和PMOS之间，在n型杂质区的上表​​面形成n +型杂质区。 电极位于n +型杂质区域，电极连接到高压侧浮动电源绝对电压（VB）。

公开(公告)号：US07977787B2

公开(公告)日：2011-07-12

申请号：US12332409

申请日：2008-12-11

申请人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

发明人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

摘要翻译： 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

公开(公告)号：US07481885B2

公开(公告)日：2009-01-27

申请号：US11412990

申请日：2006-04-28

申请人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

发明人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

IPC分类号： B05C5/02

CPC分类号： H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which ejects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

摘要翻译： 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

公开(公告)号：US20090096091A1

公开(公告)日：2009-04-16

申请号：US12332409

申请日：2008-12-11

申请人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

发明人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

IPC分类号： H01L23/48 ,  H01L21/66

CPC分类号： H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

摘要翻译： 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

公开(公告)号：US08609443B2

公开(公告)日：2013-12-17

申请号：US13666473

申请日：2012-11-01

申请人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

发明人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

IPC分类号： H01L21/66

CPC分类号： H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

摘要翻译： 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部分的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。