公开(公告)号：US06429713B2

公开(公告)日：2002-08-06

申请号：US09790672

申请日：2001-02-23

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： H03K3289

CPC分类号： H03K3/0372

摘要： A D-FF circuit for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit, wherein the clock signal generating circuit generates the plurality of clock signals at different timings, the slave flip-flop starts operating in accordance with a clock signal which is generated at an earlier timing than another clock signal generated by the clock signal generating circuit, and the master flip-flop stops operating in accordance with a clock signal which is generated at a later timing than another clock signal generated by the clock signal generating circuit.

摘要翻译： 一种D-FF电路，用于根据由时钟信号发生电路产生的多个时钟信号在每个预定定时操作主触发器和从触发器，其中时钟信号发生电路产生多个时钟信号 在不同的定时，从触发器根据在比由时钟信号发生电路产生的另一时钟信号更早的时间产生的时钟信号开始工作，并且主触发器根据时钟信号停止工作 其在比由时钟信号发生电路产生的另一个时钟信号更晚的时间产生。

公开(公告)号：US06388473B1

公开(公告)日：2002-05-14

申请号：US09605335

申请日：2000-06-27

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： H03K19082

CPC分类号： H03K19/01707 ,  H03K19/00323 ,  H03K19/0948

摘要： A logic product circuit having a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output terminal. The transistors in each column are connected in a line, forming a transistor array, the transistor arrays are connected in parallel between the output terminal and the ground, each of the input terminals is connected to the inputs to the transistors in all the columns, and the transistors to which each input terminal is connected are arranged in different rows.

摘要翻译： 一种具有以矩阵排列的多个晶体管的逻辑积电路; 多个输入端子; 和单个输出端子。 每列中的晶体管以一条线连接，形成晶体管阵列，晶体管阵列并联连接在输出端和地之间，每个输入端连接到所有列中的晶体管的输入端，以及 每个输入端子连接到的晶体管布置成不同的行。

公开(公告)号：US6133744A

公开(公告)日：2000-10-17

申请号：US637603

申请日：1996-04-25

申请人： Masayuki Yojima ,  Tohru Tsujide ,  Kazuo Nakaizumi

发明人： Masayuki Yojima ,  Tohru Tsujide ,  Kazuo Nakaizumi

IPC分类号： G01R1/073 ,  G01R31/28

CPC分类号： G01R1/07314 ,  G01R31/2886

摘要： The present invention provides a semiconductor wafer tester including a substrate, at least one chip mounted on an upper surface of the substrate, the chip having function as a tester, the chip being electrically connected to a contact formed on a lower surface of the substrate through an internal wiring formed in the substrate, and a contact film having at least one first bump formed on an upper surface thereof and at least one second bump formed on a lower surface thereof, the first bump being electrically connected to the second bump through an internal wiring formed throughout the contact film, the contact film being to be disposed to be sandwiched between the substrate and a semiconductor wafer to be tested so that the first bump is in electrical contact with the contact of the substrate and the second bump is in electrical contact with the semiconductor wafer. The tester makes it possible to carry out high frequency test concurrently for a plurality of semiconductor wafers in a shorter period of time with lower costs.

摘要翻译： 本发明提供了一种半导体晶片测试仪，其包括：基板，安装在基板的上表面上的至少一个芯片，具有作为测试器功能的芯片，该芯片电连接到形成在基板的下表面上的触点， 形成在所述基板中的内部布线，以及接触膜，其具有形成在其上表面上的至少一个第一凸块和形成在其下表面上的至少一个第二凸块，所述第一凸块通过内部电连接到所述第二凸块 布线形成在整个接触膜上，接触膜被设置为夹在基片和被测半导体晶片之间，使得第一凸起与基片与第二凸块的接触电接触， 与半导体晶圆。 测试仪可以在更短的时间内以较低的成本对多个半导体晶片同时进行高频测试。

公开(公告)号：US5058059A

公开(公告)日：1991-10-15

申请号：US528986

申请日：1990-05-25

申请人： Masahiko Matsuo ,  Kazuo Nakaizumi

发明人： Masahiko Matsuo ,  Kazuo Nakaizumi

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/787 ,  G11C29/832

摘要： A memory circuit having a regular memory cell group, a redundant memory cell group, and an improved redundant decoder circuit for selecting the redundant memory cell group if there is any defect in the regular memory cell group. The redundant decoder circuit includes first and second programming circuits, and it is inoperative when the first programming circuit has not been programmed, operative when the first program element has been programmed and the second programming circuit has not been programmed, and inoperative when the second program circuit has been programmed.

公开(公告)号：US4933903A

公开(公告)日：1990-06-12

申请号：US357460

申请日：1989-05-26

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： G11C11/417 ,  G11C11/419

CPC分类号： G11C11/419

摘要： A static semiconductor memory device having an improved write circuit which can perform a write operation at a high speed is disclosed. The memory device comprises a plurality of memory cells each having a flip-flop holding a first level and a second level lower than the first level and a write circuit for operatively generating a write data signal which is applied to a selected one of the memory cells, the write data signal selectively assuming a low level of write data signal which is lower than the second level.

摘要翻译： 公开了一种具有能够高速执行写入操作的改进的写入电路的静态半导体存储器件。 存储器件包括多个存储器单元，每个存储器单元具有保持第一电平和比第一电平低的第二电平的触发器;以及写电路，用于可操作地产生施加到所选择的一个存储单元的写数据信号 写数据信号选择性地假设低于第二电平的写数据信号的低电平。

公开(公告)号：US4672583A

公开(公告)日：1987-06-09

申请号：US620984

申请日：1984-06-15

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： G11C29/02 ,  G11C7/00

CPC分类号： G11C29/02

摘要： A dynamic random access memory device is equipped with a test circuit for testing an internal refresh circuit. In a test mode, the content of an internal address counter is supplied to both the row of column address decoders, by which one memory cell disposed on the diagonal in a memory cell array is designated. Further, data is written into the designated memory cell from outside of the memory device, and the data stored in the designated memory cell is then read out to check whether the read-out signal is coincident with the written data.

摘要翻译： 动态随机存取存储器装置配备有用于测试内部刷新电路的测试电路。 在测试模式中，将内部地址计数器的内容提供给列地址解码器行，由此指定位于存储单元阵列中的对角线上的一个存储单元。 此外，从存储装置的外部将数据写入指定的存储单元，然后读出存储在指定的存储单元中的数据，以检查读出的信号是否与写入的数据一致。

公开(公告)号：US06031382A

公开(公告)日：2000-02-29

申请号：US544582

申请日：1995-10-18

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  G01R31/02

CPC分类号： G01R31/318516 ,  G01R31/2831

摘要： A tester for integrated circuits, includes a testing set for supplying inputs for operating an integrated circuit to be tested and for measuring outputs of the integrated circuit to be tested, a semiconductor chip or wafer formed with at least some of the functions of the testing set, and a contact member through which the semiconductor chip or wafer is to come into electrical contact with the integrated circuit to be tested. Thus, it is not necessary to transmit test signals from the testing set, and hence it is possible to simplify the expensive hardware necessary for transmitting the test signals. As a result, the cost of the tester is markedly reduced.

摘要翻译： 一种用于集成电路的测试器，包括用于提供用于操作待测试的集成电路的输入和用于测量待测试的集成电路的输出的测试装置，形成有测试装置的至少一些功能的半导体芯片或晶片 以及半导体芯片或晶片通过其与要测试的集成电路电接触的接触构件。 因此，不需要从测试装置发送测试信号，因此可以简化传输测试信号所需的昂贵的硬件。 结果，测试仪的成本显着降低。

公开(公告)号：US4982111A

公开(公告)日：1991-01-01

申请号：US294707

申请日：1989-01-09

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： G11C11/417 ,  H03K3/012 ,  H03K3/356

CPC分类号： H03K3/356026 ,  H03K3/012

摘要： For prompt response to an alternation of input signal, a latching circuit comprises two NAND gates each responsive to the input signal or the inverse thereof as well as an enable signal to produce an output signal or the inverse thereof, two level shifting circuits operative to shift the output signal and the inverse thereof in voltage level, and the controller providing a voltage level to partially define the shifting range of the output signal, and each of the level shifting circuits has a capacitor and two level shifters connected to the capacitor and the controller, respectively, so that the controller has no affection of the capacitor, thereby allowing the latching operation to be improved in speed.

公开(公告)号：US4878201A

公开(公告)日：1989-10-31

申请号：US149269

申请日：1988-01-28

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： G11C7/10 ,  G11C7/22

CPC分类号： G11C7/1033 ,  G11C7/22

摘要： A drive timing signal generator for generating a drive timing signal used for driving transfer gate transistors in a memory device, is disclosed. The generator includes a boost circuit for operative generating a boosted voltage above the power voltage and an additional boost circuit for further boosting the boosted voltage generated by the boost circuit after the generation of the boosted voltage in a write mode.

公开(公告)号：US4688196A

公开(公告)日：1987-08-18

申请号：US647573

申请日：1984-09-06

申请人： Yasaburo Inagaki ,  Kazuo Nakaizumi

发明人： Yasaburo Inagaki ,  Kazuo Nakaizumi

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： The semiconductor memory device includes an internal refresh circuit and an input circuit composed of first and second transistors of a different conductivity type having gates connected in common to an external control signal input terminal and connected in series with each other. A third transistor is connected in series to the first and second transistors. The third transistor is deactivated when the internal refresh circuit, operates to carry out a self-refresh mode, thereby suppressing a power consumption in the input circuit.

摘要翻译： 半导体存储器件包括内部刷新电路和由不同导电类型的第一和第二晶体管组成的输入电路，其具有与外部控制信号输入端子共同连接并彼此串联连接的栅极。 第三晶体管与第一和第二晶体管串联连接。 当内部刷新电路进行自刷新模式时，第三晶体管被去激活，从而抑制输入电路的功耗。