公开(公告)号：US06459303B1

公开(公告)日：2002-10-01

申请号：US09829499

申请日：2001-04-09

申请人： Wanli Chang ,  David Jefferson

发明人： Wanli Chang ,  David Jefferson

IPC分类号： H03K19082

CPC分类号： G11C8/10

摘要： A high-performance address decoder circuit provides higher speed read and write access for an embedded memory of a programmable logic integrated circuit. The address decoder is programmable to allow addressing of the memory in different data widths and depths. The circuitry can be used as column address decoder or row address decoder, or both. In a dual-port memory implementation of the memory, there can be two instances of each of the decoders, one for writing and one for reading.

摘要翻译： 高性能地址解码器电路为可编程逻辑集成电路的嵌入式存储器提供更高速度的读和写访问。 地址解码器是可编程的，以允许以不同的数据宽度和深度寻址存储器。 电路可以用作列地址解码器或行地址解码器，或两者兼有。 在存储器的双端口存储器实现中，每个解码器可以有两个实例，一个用于写入，一个用于读取。

公开(公告)号：US06424172B1

公开(公告)日：2002-07-23

申请号：US09796996

申请日：2001-02-28

申请人： Valerio Pisati ,  Salvatore Portaluri ,  Marco Cazzaniga ,  Rinaldo Castello

发明人： Valerio Pisati ,  Salvatore Portaluri ,  Marco Cazzaniga ,  Rinaldo Castello

IPC分类号： H03K19082

CPC分类号： H03H11/0422

摘要： This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor. Thus, a released “zero” can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.

摘要翻译： 本发明涉及具有可编程零点的前馈类型的电路结构，特别是用于合成时间连续滤波器。 该结构包括互连至少一个互连节点并连接在第一单元的第一信号输入和第二单元的输出端之间的一对放大单元，每个单元包括一对具有共同的导通端子并具有 其它导电端子通过相应的偏置构件分别耦合到第一电压基准。 所述结构还包括将所述第一单元的节点连接到所述输出端子并且包括具有连接到所述第一单元的节点的控制端子的晶体管，连接到所述输出端子的第一导通端子和第二导通 端子通过电容器耦合到第二参考电压。 因此，可以在极零复平面的右半平面中引入释放的“零”，以改善组增益的平坦化。

公开(公告)号：US06593778B1

公开(公告)日：2003-07-15

申请号：US09655275

申请日：2000-09-05

申请人： Sandeep G. Bharathi

发明人： Sandeep G. Bharathi

IPC分类号： H03K19082

CPC分类号： H03K19/0963 ,  G06F7/57

摘要： A zero detect circuit. The zero detect circuit includes a data-driven intermediate precharge device coupled to each of a plurality of data inputs to precharge an internal node in response to a data signal received via the corresponding data input. An output responsive to the data signals and to a first clock signal indicates whether all of the data signals represent logical zero data.

摘要翻译： 零检测电路。 零检测电路包括耦合到多个数据输入中的每一个的数据驱动中间预充电装置，以响应于经由相应数据输入接收的数据信号对内部节点进行预充电。 响应于数据信号和第一时钟信号的输出指示所有数据信号是否表示逻辑零数据。

公开(公告)号：US06593777B2

公开(公告)日：2003-07-15

申请号：US10141621

申请日：2002-05-08

申请人： Thomas Alofs

发明人： Thomas Alofs

IPC分类号： H03K19082

CPC分类号： H03K17/005 ,  H03K3/037

摘要： A multiplexed flip-flop electronic device includes a decoder logic circuit for providing a first switching signal, and a control circuit for receiving a clock signal and for providing a gated clock signal forming a second switching signal. The electronic device further includes a multiplexing circuit having N inputs and an output, and a flip flop circuit. The flip-flop circuit includes a first switching stage connected between the N inputs and the output of the multiplexing circuit, and includes N switches being individually controlled by the first switching signal. A first buffer stage is connected to the output of the multiplexing circuit, and a second switching stage is connected to an output of the first buffer stage. The second switching stage is controlled by the second switching signal. A second buffer stage is connected to an output of the second switching stage.

公开(公告)号：US06172523B2

公开(公告)日：2001-01-09

申请号：US09163431

申请日：1998-09-30

申请人： Martin Blaszczyk ,  Vincent E. Bridge ,  Daniel E. Radke ,  Brent E. Taylor ,  Michael Zurat

发明人： Martin Blaszczyk ,  Vincent E. Bridge ,  Daniel E. Radke ,  Brent E. Taylor ,  Michael Zurat

IPC分类号： H03K19082

CPC分类号： H03K19/0175 ,  H04L25/028

摘要： A system and method for translating a non-logic-family signal level into a logic-family signal level, the system comprising: a source of a non-logic-family signal that can assume a first and a second non-logic-family state; and a translator for determining whether the signal is in the first non-logic-family state, and if so, providing a translated signal having a first-logic family level. The translator can take the form of a comparator controlling an output transistor tied to a pull-up resistor, or a programmed processor. Examples of the logic-families include transistor-transistor logic (TTL) and complimentary metal oxide semiconductor (CMOS) logic. Examples of sources of non-logic-family signals includes a light emitting diode, a buzzer and a beeping device.

摘要翻译： 一种用于将非逻辑系列信号电平转换为逻辑系列信号电平的系统和方法，所述系统包括：非逻辑系列信号的源，其可以采用第一和第二非逻辑系列状态 ; 以及用于确定信号是否处于第一非逻辑系列状态的翻译器，如果是，则提供具有第一逻辑系列级的转换信号。 转换器可以采用比较器的形式来控制与上拉电阻器或编程处理器相连的输出晶体管。 逻辑系列的例子包括晶体管晶体管逻辑（TTL）和互补金属氧化物半导体（CMOS）逻辑。 非逻辑系列信号源的示例包括发光二极管，蜂鸣器和蜂鸣器。

公开(公告)号：US06762623B2

公开(公告)日：2004-07-13

申请号：US10320148

申请日：2002-12-16

申请人： Samudyatha Suryanarayana ,  Aninda K. Roy

发明人： Samudyatha Suryanarayana ,  Aninda K. Roy

IPC分类号： H03K19082

CPC分类号： H04L25/0292

摘要： Disclosed are novel methods and apparatus for efficiently providing high-resolution single-ended source synchronous receivers. In an embodiment of the present invention, a source-synchronous receiver is disclosed. The receiver includes: a first amplifier to receive a clock signal and a data signal, the first amplifier providing a first output signal; a second amplifier to receive a complementary clock signal and the data signal, the second amplifier providing a second output signal; a third amplifier to receive the clock signal and the data signal, the third amplifier providing a third output signal, the second and third output signals being combined to provide a fifth output; and a fourth amplifier to receive the complementary clock signal and the data signal, the fourth amplifier providing a fourth output signal, the first and fourth output signals being combined to provide a sixth output signal.

摘要翻译： 公开了用于有效提供高分辨率单端源同步接收机的新颖方法和装置。 在本发明的实施例中，公开了一种源同步接收机。 所述接收机包括：第一放大器，用于接收时钟信号和数据信号，所述第一放大器提供第一输出信号; 第二放大器，用于接收互补时钟信号和所述数据信号，所述第二放大器提供第二输出信号; 第三放大器，用于接收所述时钟信号和所述数据信号，所述第三放大器提供第三输出信号，所述第二和第三输出信号被组合以提供第五输出; 以及第四放大器，用于接收所述互补时钟信号和所述数据信号，所述第四放大器提供第四输出信号，所述第一和第四输出信号被组合以提供第六输出信号。

公开(公告)号：US06636077B1

公开(公告)日：2003-10-21

申请号：US09330875

申请日：1999-06-11

申请人： Charles E. Chang ,  Andre Metzger

发明人： Charles E. Chang ,  Andre Metzger

IPC分类号： H03K19082

CPC分类号： H03K17/6264

摘要： A high-isolation, low-power high-speed multiplexer circuit suitably includes a buffer stage and a current steering tree stage. By employing common select lines for both stages of the circuit, both the input buffer and the deselected channel provide cumulative isolation for the deselected channels.

摘要翻译： 高隔离，低功率高速多路复用器电路适当地包括缓冲器级和当前转向树级。 通过对电路的两个阶段采用公共选择线，输入缓冲器和取消选择的通道都为未选通道提供累积隔离。

公开(公告)号：US06400181B1

公开(公告)日：2002-06-04

申请号：US09622683

申请日：2000-10-16

申请人： Christoph Joch

发明人： Christoph Joch

IPC分类号： H03K19082

CPC分类号： H03K19/01806

摘要： In a method and in a circuit arrangement for transmitting signals from an output of a first circuit to an input of a second circuit, where the circuits have a first and a second operating voltage and a first and a second ground potential applied to them, and where variable potential differences can arise between the ground potentials. A current controlled by the signal which is to be transmitted flows from the output of the first circuit to a circuit point having a further potential applied to it and controls a further current, which emanates from the circuit point and is supplied to the input of the second circuit, and the further potential is chosen such that a respective voltage enabling the current and the further current is present between the output of the first circuit and the further potential, on the one hand, and between the further potential and the input of the second circuit, on the other hand, for the potential differences which arise.

摘要翻译： 在用于将信号从第一电路的输出传输到第二电路的输入的方法和电路装置中，其中电路具有施加到它们的第一和第二工作电压和第一和第二地电位，以及 其中地电位之间可能产生可变电位差。 由要发送的信号控制的电流从第一电路的输出流向具有施加到其上的另外的电位的电路点，并且控制从电路点发出的另外的电流，并被提供给 第二电路，并且进一步的电位被选择为使得能够在第一电路的输出和另一个电位之间以及另一个电位和另一个电流的输入之间存在实现电流和另外的电流的相应电压 另一方面，第二电路出现的电位差。

公开(公告)号：US06388473B1

公开(公告)日：2002-05-14

申请号：US09605335

申请日：2000-06-27

申请人： Kazuo Nakaizumi

发明人： Kazuo Nakaizumi

IPC分类号： H03K19082

CPC分类号： H03K19/01707 ,  H03K19/00323 ,  H03K19/0948

摘要： A logic product circuit having a plurality of transistors arranged in a matrix; a plurality of input terminals; and a single output terminal. The transistors in each column are connected in a line, forming a transistor array, the transistor arrays are connected in parallel between the output terminal and the ground, each of the input terminals is connected to the inputs to the transistors in all the columns, and the transistors to which each input terminal is connected are arranged in different rows.

摘要翻译： 一种具有以矩阵排列的多个晶体管的逻辑积电路; 多个输入端子; 和单个输出端子。 每列中的晶体管以一条线连接，形成晶体管阵列，晶体管阵列并联连接在输出端和地之间，每个输入端连接到所有列中的晶体管的输入端，以及 每个输入端子连接到的晶体管布置成不同的行。