-
公开(公告)号：US07716391B2
公开(公告)日：2010-05-11
申请号：US11382379
申请日：2006-05-09
申请人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
发明人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
IPC分类号： G06F3/00
CPC分类号： G06F3/0221 , G06F13/28 , Y02D10/14
摘要： A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.
摘要翻译： 根据本发明的数据传送装置具有： DMAC和另一个DMAC，其通过多个总线之间的直接存储器访问来传送数据; 作为队列保存用于指示数据传送的命令的命令队列; 总线信息获取单元，其从命令队列获取命令; 分组单元，其基于在每个所获得的命令中指定的源和目的地对保持的命令进行分组; 作为优先级，从具有更多命令的组中顺序地确定发出命令的顺序的调度单元; 以及选择器，其根据所决定的顺序选择要发出的命令。
-
公开(公告)号：US20060259662A1
公开(公告)日：2006-11-16
申请号：US11382379
申请日：2006-05-09
申请人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
发明人： Kazuya Furukawa , Nobuo Higaki , Hideyo Tsuruta , Kazushi Kurata , Shigeki Fujii , Kousuke Yoshioka , Hiroyuki Morishita
IPC分类号： G06F3/00
CPC分类号： G06F3/0221 , G06F13/28 , Y02D10/14
摘要： A data transfer apparatus according to the present invention has; a DMAC and another DMAC which transfer data by direct memory access among a plurality of buses; a command queue which holds, as a queue, commands for instructing the data transfer; a bus information obtainment unit which obtains the commands from the command queue; a grouping unit which groups the held commands, based on a source and a destination designated in each of the obtained commands; a schedule unit which decides an order of issuing the commands sequentially from a group having more command, as a priority; and a selector which selects a command to be issued according to the decided order.
摘要翻译： 根据本发明的数据传送装置具有： DMAC和另一个DMAC，其通过多个总线之间的直接存储器访问来传送数据; 作为队列保存用于指示数据传送的命令的命令队列; 总线信息获取单元，其从命令队列获取命令; 分组单元，其基于在每个所获得的命令中指定的源和目的地对保持的命令进行分组; 作为优先级，从具有更多命令的组中顺序地确定发出命令的顺序的调度单元; 以及选择器，其根据所决定的顺序选择要发出的命令。
-
公开(公告)号：US20090037779A1
公开(公告)日：2009-02-05
申请号：US11916319
申请日：2006-06-06
申请人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
发明人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
CPC分类号： G06F13/385
摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.
摘要翻译： 响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到 并将写入数据写入由写入地址指定的外部设备。 当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。
-
公开(公告)号：US07685351B2
公开(公告)日：2010-03-23
申请号：US11916319
申请日：2006-06-06
申请人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
发明人： Takao Kawakami , Masaitsu Nakajima , Tokuzo Kiyohara , Hiroyuki Morishita , Nobuo Higaki , Yousuke Kudo
IPC分类号： G06F13/00
CPC分类号： G06F13/385
摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.
摘要翻译： 响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到 并将写入数据写入由写入地址指定的外部设备。 当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。
-
公开(公告)号：US09317287B2
公开(公告)日：2016-04-19
申请号：US14232389
申请日：2012-06-06
申请人： Hiroyuki Morishita
发明人： Hiroyuki Morishita
CPC分类号： G06F9/30145 , G06F9/30185 , G06F9/3836 , G06F9/3877 , G06F11/362
摘要： To provide a multi-processor system that efficiently debugs operations of one processor and operations of another processor. The multiprocessor system has a first processor and a second processor that executes processing by receiving notification from the first processor. The first processor: sequentially specifies instructions to be executed from an instruction queue; sends a notification based on a processing request instruction to the second processor when an instruction that is specified is the processing request instruction; executes the instruction that is specified when the instruction that is specified is not the processing request instruction; and determines whether or not a debug mode is set. When the first processor determines that the debug mode is set, the first processor stops specifying instructions after specifying the processing request instruction, and, after sending the notification, resumes specifying instructions after detecting that the second processor has completed processing corresponding to the notification.
摘要翻译： 提供有效调试一个处理器的操作和另一个处理器的操作的多处理器系统。 多处理器系统具有通过从第一处理器接收通知来执行处理的第一处理器和第二处理器。 第一处理器：从指令队列中顺序指定要执行的指令; 当指定的指令是处理请求指令时，基于处理请求指令向第二处理器发送通知; 当指定的指令不是处理请求指令时执行指定的指令; 并确定是否设置了调试模式。 当第一处理器确定调试模式被设置时，第一处理器在指定处理请求指令之后停止指定指令，并且在发送通知之后，在检测到第二处理器已经完成与通知相对应的处理之后恢复指定指令。
-
6.发明授权公开(公告)号：US09201899B2
公开(公告)日：2015-12-01
申请号：US13824865
申请日：2012-09-11
CPC分类号： G06F17/30244 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the register group and reading the elements in the same column by using column position information indicating positions in the register group at which the elements in the same column are stored; an input data rearrangement unit rearranging the read elements; an operation unit performing an operation on the rearranged elements; and a transposition control unit generating rearrangement information and the column position information to control rearrangement, and performs transposition at high speed by performing rearrangement at the time of storing/reading data in/from the register group.
摘要翻译： 移位操作装置包括：存储数据矩阵的寄存器组，使得元素一次可读; 输出数据重排单元重新排列矩阵的每行中的元素，使得矩阵的同一列中的元素在重新排列之后处于矩阵的不同列中; 寄存器访问单元，通过使用指示存储同一列中的元素的寄存器组中的位置的列位置信息，将重排后的矩阵写入寄存器组并读取同一列中的元素; 输入数据重排单元重新排列读取的元件; 对重新排列的元件执行操作的操作单元; 以及转置控制单元，其生成重排信息和列位置信息以控制重排，并且通过在从寄存器组中存储/读取数据时执行重排来高速执行转置。
-
公开(公告)号：US07926055B2
公开(公告)日：2011-04-12
申请号：US11574359
申请日：2006-04-12
IPC分类号： G06F9/46
CPC分类号： G06F15/7867 , G06F9/30076 , G06F9/3851 , G06F9/3867 , G06F9/3885 , G06F9/3897
摘要： The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.
摘要翻译： 本发明提供了一种根据分配给每个线程的执行时间循环地执行多个线程的处理器，包括可重构集成电路。 处理器存储分别对应于多个线程的电路配置信息集合，基于电路配置信息集重配置集成电路的一部分，并且使用基于配置信息之一重新配置的集成电路来顺序地执行每个线程 设置对应于线程。 在执行给定的线程的同时，处理器根据与所选择的线程对应的电路配置信息，选择要执行的线程，并重新配置当前不用于执行给定线程的集成电路的一部分。
-
公开(公告)号：US20070028055A1
公开(公告)日：2007-02-01
申请号：US10571531
申请日：2004-08-23
IPC分类号： G06F12/00
CPC分类号： G06F12/127 , G06F12/124
摘要： A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding to the hit cache entry so that the use flag U indicates that the cache entry has been accessed; and reset, in the case where all other use flags in the same set indicates that the cache entries have been accessed herein, the all other use flags so that the use flags indicate that the cache entries have not been accessed; and select a cache entry to be replaced from among the cache entries corresponding to the use flags indicating that the cache entries have not been accessed.
摘要翻译： 本发明的高速缓存存储器包括：对于每个高速缓存条目，方式0到路径3，其保持使用标志U，指示是否已经访问了使用标志U; 以及控制单元，其在高速缓存条目被命中时更新与所述命中高速缓存条目对应的使用标志U，使得所述使用标志U指示所述高速缓存条目已经被访问; 并且在同一集合中的所有其他使用标志指示已经在这里访问了高速缓存条目的情况下，复位所有其他使用标志，使得使用标志指示高速缓存条目未被访问; 并且从与指示高速缓存条目未被访问的使用标志相对应的高速缓存条目中选择要替换的高速缓存条目。
-
公开(公告)号：US06233948B1
公开(公告)日：2001-05-22
申请号：US09504385
申请日：2000-02-15
申请人： Hiroyuki Morishita , Satoru Uosaki
发明人： Hiroyuki Morishita , Satoru Uosaki
IPC分类号： B01D800
CPC分类号： F04B49/00 , F04B37/08 , F25B9/10 , F25B49/02 , F25B2309/002 , Y10S417/901
摘要： For simultaneously controlling a plurality of cryopumps, one processor and communication conversion sections of the respective cryopumps are connected to each other with a communication network. The processor and a host computer are connected to each other with an exclusive line. The processor controls the cryopumps in time division by performing data exchange with the communication conversion sections of the cryopumps by means of packet exchange, line exchange and the like via the communication network. Thus, the need of providing exclusive processors for the cryopumps, respectively, is eliminated, allowing a large extent of cost reduction as well as a wiring simplification to be realized.
摘要翻译： 为了同时控制多个低温泵，各个低温泵的一个处理器和通信转换部分通过通信网络相互连接。 处理器和主机通过专用线相互连接。 处理器通过经由通信网络的分组交换，线路交换等与低温泵的通信转换部分进行数据交换来对时间分割进行控制。 因此，分别为低温泵提供专用处理器的需要被消除，从而允许大量的成本降低以及实现布线简化。
-
10.发明申请TRANSPOSITION OPERATION DEVICE, INTEGRATED CIRCUIT FOR THE SAME, AND TRANSPOSITION METHOD 有权传输操作装置，用于其的集成电路和传输方法公开(公告)号：US20140003742A1
公开(公告)日：2014-01-02
申请号：US13824865
申请日：2012-09-11
IPC分类号： G06F17/30
CPC分类号： G06F17/30244 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： A transposition operation device includes: a register group storing a matrix of data such that elements are readable one at a time; an output data rearrangement unit rearranging elements in each row of the matrix so that elements in a same column of the matrix are in different columns of the matrix after rearrangement; a register access unit writing the matrix after rearrangement to the register group and reading the elements in the same column by using column position information indicating positions in the register group at which the elements in the same column are stored; an input data rearrangement unit rearranging the read elements; an operation unit performing an operation on the rearranged elements; and a transposition control unit generating rearrangement information and the column position information to control rearrangement, and performs transposition at high speed by performing rearrangement at the time of storing/reading data in/from the register group.
摘要翻译： 移位操作装置包括：存储数据矩阵的寄存器组，使得元素一次可读; 输出数据重排单元重新排列矩阵的每行中的元素，使得矩阵的同一列中的元素在重新排列之后处于矩阵的不同列中; 寄存器访问单元，通过使用指示存储同一列中的元素的寄存器组中的位置的列位置信息，将重排后的矩阵写入寄存器组并读取同一列中的元素; 输入数据重排单元重新排列读取的元件; 对重新排列的元件执行操作的操作单元; 以及转置控制单元，其生成重排信息和列位置信息以控制重排，并且通过在从寄存器组中存储/读取数据时执行重新排列而高速执行转置。
-
-
-
-
-
-
-
-
-
搜索结果
37 条记录 (耗时 0.033 秒)
