Fabrication method of semiconductor integrated circuit device
    1.
    发明授权
    Fabrication method of semiconductor integrated circuit device 有权
    半导体集成电路器件的制造方法

    公开(公告)号:US06797442B2

    公开(公告)日:2004-09-28

    申请号:US10614789

    申请日:2003-07-09

    IPC分类号: G03F900

    CPC分类号: G03F7/70558

    摘要: An average value of dimensions of resist patterns formed each time exposure processing is effected on semiconductor substrates of a predetermined number of lots, is compared with a target dimension. When a drift between each of the dimensions of the formed resist patterns and the target dimension is larger than a first value, exposure energy is corrected with a relatively large correction value &agr;1. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the first value and larger than a second value, exposure energy is corrected with a relatively small correction value &agr;2. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the second value, no exposure energy is corrected. Exposure processing is effected on a semiconductor substrate of the next lot by using the calculated exposure energy.

    摘要翻译: 将在预定批次的半导体衬底上进行每次曝光处理形成的抗蚀剂图案的尺寸的平均值与目标尺寸进行比较。 当形成的抗蚀剂图案的每个尺寸和目标尺寸之间的漂移大于第一值时,以相对大的校正值α1校正曝光能量。 当形成的抗蚀剂图案的每个尺寸与目标尺寸之间的漂移小于第一值并且大于第二值时,以相对较小的校正值α2校正曝光能量。 当形成的抗蚀剂图案的每个尺寸和目标尺寸之间的漂移小于第二值时,不会校正曝光能量。 通过使用计算出的曝光能量对下一批次的半导体衬底进行曝光处理。