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公开(公告)号：US07613961B2
公开(公告)日：2009-11-03
申请号：US10685177
申请日：2003-10-14
IPC分类号： G11C29/00 , G06F11/00 , G06F13/00 , G06F13/28 , G06F7/38 , G06F9/44 , G06F17/50 , G06F11/30 , G21C17/00 , G06G7/62
CPC分类号： G06F11/263
摘要： One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.
摘要翻译： 公开的一个实施例涉及一种编译要在目标中央处理单元（CPU）上执行的程序的方法。 该方法包括机会性调度CPU寄存器的诊断测试。 该方法可以包括使用预定级别的侵略性来进行寄存器诊断测试的调度。 计划的诊断测试可以包括将已知数据写入寄存器，从寄存器读取数据，以及将已知数据与所读取的数据进行比较。 如果比较表示差异，则故障处理程序可能发生跳转。
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2.发明授权公开(公告)号：US06933853B2
公开(公告)日：2005-08-23
申请号：US10459853
申请日：2003-06-12
CPC分类号： G01R31/046
摘要： One embodiment disclosed relates to a printed circuit assembly (PCA) with built-in circuitry to detect and communicate an interconnect failure. The PCA includes a connector, a continuity detect circuit, and an interface circuit. The connector is configured to interconnect to an electronic unit. The continuity detect circuit is coupled to the connector for detection of continuity failure in the interconnect. The interface circuit is coupled to the continuity detect circuit for communicating data pertaining to status of the interconnect to system management.
摘要翻译： 所公开的一个实施例涉及一种具有内置电路以检测和传送互连故障的印刷电路组件（PCA）。 PCA包括连接器，连续性检测电路和接口电路。 连接器被配置为与电子单元互连。 连续性检测电路耦合到连接器，用于检测互连中的连续性故障。 接口电路耦合到连续性检测电路，用于将与互连状态有关的数据传送到系统管理。
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公开(公告)号：US07415700B2
公开(公告)日：2008-08-19
申请号：US10684842
申请日：2003-10-14
IPC分类号： G06F9/44
CPC分类号： G06F11/2242
摘要： One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of program code and diagnostics code. The diagnostic code is scheduled to be executed on the selected execution unit. The program code is scheduled to be executed on remaining execution units of the same type.
摘要翻译： 公开的一个实施例涉及一种编译要在具有相同类型的多个执行单元的目标微处理器上执行的程序的方法。 该方法包括选择一个执行单元，用于测试和调度程序代码和诊断代码的并行执行。 诊断代码被调度为在所选执行单元上执行。 程序代码被安排在相同类型的剩余执行单元上执行。
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公开(公告)号：US07146530B2
公开(公告)日：2006-12-05
申请号：US10623099
申请日：2003-07-18
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F9/30181
摘要： One embodiment disclosed relates to a microprocessor for targeted fault-tolerant computing. The microprocessor's decode circuitry is configured to decode a fault-tolerant version of an instruction and a non-fault-tolerant version of the instruction distinctly from each other. The microprocessor's execution circuitry is configured to execute the fault-tolerant version of the instruction with redundancy checking and to execute the non-fault-tolerant version of the instruction without redundancy checking.
摘要翻译： 所公开的一个实施例涉及用于目标容错计算的微处理器。 微处理器的解码电路被配置为对指令的容错版本和指令的非容错版本彼此明确地进行解码。 微处理器的执行电路被配置为执行具有冗余校验的指令的容错版本，并执行指令的非容错版本而不进行冗余校验。
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5.发明授权Method and apparatus for automatically evaluating and allocating resources in a cell based system 有权用于在基于单元的系统中自动评估和分配资源的方法和装置公开(公告)号：US07586946B2
公开(公告)日：2009-09-08
申请号：US11263502
申请日：2005-10-31
IPC分类号： H04J3/22
CPC分类号： H04L69/40 , H04L43/50 , H04L47/14 , H04L47/15 , H04L47/70 , H04L47/762 , H04L47/781 , H04L47/822 , H04L47/826 , H04L49/354 , H04L67/1002 , H04L67/1008
摘要： Embodiments of the invention provide a method and apparatus for automatically evaluating and allocating resources in a cell based system. In one method embodiment, the present invention receives a request to generate a cell based system of resources. A list of allocatable resources having corresponding evaluation data is then accessed. The request for the cell based system is then compared with the list of allocatable resources having corresponding evaluation data. The allocatable resources are then assigned to the cell based system.
摘要翻译： 本发明的实施例提供一种用于在基于小区的系统中自动评估和分配资源的方法和装置。 在一个方法实施例中，本发明接收生成基于小区的资源系统的请求。 然后访问具有相应评估数据的可分配资源的列表。 然后将基于小区的系统的请求与具有相应评估数据的可分配资源的列表进行比较。 然后将可分配资源分配给基于单元的系统。
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公开(公告)号：US07213170B2
公开(公告)日：2007-05-01
申请号：US10659079
申请日：2003-09-10
IPC分类号： G06F11/00
CPC分类号： G06F11/1641 , G06F11/2236
摘要： One embodiment disclosed relates to a method of providing CPU functional testing. Operations are executed on multiple functional units of a same type in the CPU. The outputs of the multiple functional units are automatically compared. The results of the comparison are checked only for redundant operations. Another embodiment disclosed relates to a microprocessor with built-in functional testing capability. The microprocessor includes multiple functional units of a same type and registers that receive outputs from the multiple functional units. In addition, comparator circuitry is built-in that also receives the outputs from the multiple functional units and compares the outputs to provide functional testing.
摘要翻译： 所公开的一个实施例涉及提供CPU功能测试的方法。 在CPU中的相同类型的多个功能单元上执行操作。 自动比较多个功能单元的输出。 仅对冗余操作检查比较结果。 所公开的另一实施例涉及具有内置功能测试能力的微处理器。 微处理器包括相同类型的多个功能单元和用于接收来自多个功能单元的输出的寄存器。 此外，内置比较器电路，还可以接收多个功能单元的输出，并比较输出以提供功能测试。
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公开(公告)号：US07581210B2
公开(公告)日：2009-08-25
申请号：US10658983
申请日：2003-09-10
CPC分类号： G06F11/2236 , G06F11/1641
摘要： One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple functional units of a same type. The method includes opportunistically scheduling a redundant operation on one of the functional units that would otherwise be idle during a cycle.
摘要翻译： 所公开的一个实施例涉及一种编译要在具有相同类型的多个功能单元的目标微处理器上执行的程序的方法。 该方法包括机会地调度在一个循环中否则将是空闲的功能单元之一上的冗余操作。
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公开(公告)号：US07206969B2
公开(公告)日：2007-04-17
申请号：US10658981
申请日：2003-09-10
IPC分类号： G06F11/00
CPC分类号： G06F8/41 , G06F11/263
摘要： One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor. A cycle is identified during which a functional unit would otherwise be idle. A diagnostic operation is opportunistically scheduled for execution on the functional unit during that cycle, and a comparison is scheduled to compare a result from executing the diagnostic operation with a corresponding predetermined result.
摘要翻译： 所公开的一个实施例涉及一种编译要在目标微处理器上执行的程序的方法。 识别一个周期，在该周期期间，功能单元否则将空闲。 诊断操作被机会地安排在该周期期间在功能单元上执行，并且调度比较以将执行诊断操作的结果与相应的预定结果进行比较。
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公开(公告)号：US07206966B2
公开(公告)日：2007-04-17
申请号：US10690727
申请日：2003-10-22
IPC分类号： G06F11/00
CPC分类号： G06F11/2242
摘要： One embodiment disclosed relates to a method of executing program code on a target microprocessor with multiple CPU cores thereon. One of the CPU cores is selected for testing, and inter-core context switching is performed. Parallel execution occurs of diagnostic code on the selected CPU core and the program code on remaining CPU cores. Another embodiment disclosed relates to a microprocessor having a plurality of CPU cores integrated on the microprocessor chip. Inter-core communications circuitry is coupled to each of the CPU cores and configured to perform context switching between the CPU cores.
摘要翻译： 公开的一个实施例涉及在其上具有多个CPU核的目标微处理器上执行程序代码的方法。 选择其中一个CPU内核进行测试，并执行核心内部切换。 所选CPU核心上的诊断代码和剩余CPU内核上的程序代码并行执行。 所公开的另一实施例涉及具有集成在微处理器芯片上的多个CPU核的微处理器。 核心间通信电路耦合到每个CPU核心并被配置为执行CPU核心之间的上下文切换。
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公开(公告)号：US06919813B2
公开(公告)日：2005-07-19
申请号：US10439553
申请日：2003-05-16
CPC分类号： H05K1/0268 , G01R31/043 , G01R31/2818 , H05K1/117 , H05K2201/10037 , H05K2201/10053 , H05K2201/10106
摘要： One embodiment disclosed relates to a printed circuit board (PCB) with built-in circuitry to test connector loading. The PCB includes at least the connector to be tested, an indicator circuit, and a switch. The connector is configured to interconnect to a card. The switch couples the connector to the indicator circuit, and integrity of the interconnection between the card and the connector is indicated by the indicator circuit.
摘要翻译： 公开的一个实施例涉及具有内置电路以测试连接器负载的印刷电路板（PCB）。 PCB至少包括要测试的连接器，指示器电路和开关。 连接器被配置为与卡互连。 开关将连接器连接到指示器电路，并且指示器电路指示卡和连接器之间的互连的完整性。
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