公开(公告)号：US07299394B2

公开(公告)日：2007-11-20

申请号：US10400911

申请日：2003-03-28

申请人： Ken-ichi Ichino ,  Masayuki Arai ,  Satoshi Fukumoto ,  Kazuhiko Iwasaki ,  Takeshi Shoda ,  Masayuki Sato

发明人： Ken-ichi Ichino ,  Masayuki Arai ,  Satoshi Fukumoto ,  Kazuhiko Iwasaki ,  Takeshi Shoda ,  Masayuki Sato

IPC分类号： G01R31/28

CPC分类号： G06F11/261 ,  G01R31/3172 ,  G01R31/318342 ,  G01R31/318371

摘要： The purpose of the invention is to determine an optimum initial value to be input to a test pattern generator in order to achieve efficient testing of an integrated circuit. To achieve this purpose, a minimum test length is obtained by performing a fault simulation and a reverse-order fault simulation using an arbitrarily given initial value; the next initial value that is likely to yield a test length shorter than the minimum test length is computed and a fault simulation is performed using the thus computed initial value; and the next initial value that is likely to yield a test length shorter than that test length is computed and a fault simulation is performed using the thus computed initial value. By repeating this process, an initial value that yields the shortest test length is obtained.

摘要翻译： 本发明的目的是确定要输入到测试图案发生器的最佳初始值，以便实现集成电路的有效测试。 为了达到这个目的，通过使用任意给定的初始值执行故障模拟和反向故障模拟来获得最小测试长度; 计算可能产生比最小测试长度短的测试长度的下一个初始值，并且使用由此计算的初始值来执行故障模拟; 并且计算可能产生比该测试长度短的测试长度的下一个初始值，并且使用由此计算的初始值来执行故障模拟。 通过重复该过程，获得产生最短测试长度的初始值。

公开(公告)号：US07702979B2

公开(公告)日：2010-04-20

申请号：US11397899

申请日：2006-04-05

申请人： Masayuki Arai ,  Kazuhiko Iwasaki ,  Satoshi Fukumoto ,  Takeshi Shoda ,  Junichi Nishimoto

发明人： Masayuki Arai ,  Kazuhiko Iwasaki ,  Satoshi Fukumoto ,  Takeshi Shoda ,  Junichi Nishimoto

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318536

摘要： An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit (3) and a scan chain (2) constructed by connecting a plurality of scan flip-flops (5) in a chain, the scan chain (2) is divided into a plurality of sub scan-chains (20a to 20n) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.

摘要翻译： 本发明的一个目的是大大减少包含使用部分旋转扫描电路的测试配置的半导体集成电路中的面积开销。 为了实现这一点，在包括组合电路（3）和通过连接多个扫描触发器（5）构成的扫描链（2）的测试配置的半导体集成电路中，扫描链（2） ）被分成多个子扫描链（20a至20n），每个子扫描链具有部分旋转扫描（PRS）功能和测试响应压缩（MISR）功能。 通过在将要设置为PRS的子扫描链和将被设置为MISR的副扫描链的组合改变的同时执行多个步骤中的扫描测试，可以执行测试而不必提供测试响应压缩器 与扫描链分开，因此可以减少面积开销。

公开(公告)号：US20060282730A1

公开(公告)日：2006-12-14

申请号：US11397899

申请日：2006-04-05

申请人： Masayuki Arai ,  Kazuhiko Iwasaki ,  Satoshi Fukumoto ,  Takeshi Shoda ,  Junichi Nishimoto

发明人： Masayuki Arai ,  Kazuhiko Iwasaki ,  Satoshi Fukumoto ,  Takeshi Shoda ,  Junichi Nishimoto

IPC分类号： G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/318536

摘要： An object of the invention is to drastically reduce the area overhead in a semiconductor integrated circuit incorporating a test configuration that uses a partially rotational scan circuit. To achieve this, in the semiconductor integrated circuit incorporating the test configuration that comprises a combinational circuit (3) and a scan chain (2) constructed by connecting a plurality of scan flip-flops (5) in a chain, the scan chain (2) is divided into a plurality of sub scan-chains (20a to 20n) each of which has a partially rotational scan (PRS) function and a test response compaction (MISR) function. By performing a scan test in a plurality of steps while changing the combination of the sub scan-chains to be set as PRS and the sub scan-chains to be set as MISR, the test can be performed without having to provide a test response compactor separately from the scan chain, and thus the area overhead can be reduced.

摘要翻译： 本发明的一个目的是大大减少包含使用部分旋转扫描电路的测试配置的半导体集成电路中的面积开销。 为了实现这一点，在包括组合电路（3）和通过连接多个扫描触发器（5）构成的扫描链（2）的测试配置的半导体集成电路中，扫描链（2） ）被分成多个子扫描链（20a至20n），每个子扫描链具有部分旋转扫描（PRS）功能和测试响应压缩（MISR）功能。 通过在将要设置为PRS的子扫描链和将被设置为MISR的副扫描链的组合改变的同时执行多个步骤中的扫描测试，可以执行测试而不必提供测试响应压缩器 与扫描链分开，因此可以减少面积开销。

公开(公告)号：US08271460B2

公开(公告)日：2012-09-18

申请号：US12958350

申请日：2010-12-01

申请人： Kazuhiko Iwasaki ,  Masayuki Arai ,  Kenichi Ichino

发明人： Kazuhiko Iwasaki ,  Masayuki Arai ,  Kenichi Ichino

IPC分类号： G06F17/30

CPC分类号： G01R31/2846

摘要： A program executed on a computer including storage, processing, output, and input units, the storage unit storing test-difficulty-calculation-elements-database, test-menu-database, and test-flow-database, for each test-menu-record, the program causing the processing unit to execute: calculating test-difficulty for each test-menu-record based on test-difficulty-calculation-formula by using at least one among pieces of information indicative of relationship with netlist, the number of package/test pins, expected operational clock frequency, process technology information, power consumption, and tester storage space; identifying all relationship between DFT scheme and priority, and causing the storage unit to store information indicative of the relationship between the DFT scheme and priority into the test-flow-database; and sorting the DFT scheme in an order of the priority based on the relationship between the DFT scheme and priority, causing the storage unit to store the DFT scheme as a test flow, and causing the output unit to output the test flow.

摘要翻译： 在包括存储，处理，输出和输入单元的计算机上执行的程序，存储单元存储测试难度计算单元数据库，测试菜单数据库和测试流程数据库， 记录，使得处理单元执行的程序：基于测试难度计算公式计算每个测试菜单记录的测试难度，通过使用指示与网表的关系的信息中的至少一个，包的数量 /测试引脚，预期的工作时钟频率，工艺技术信息，功耗和测试仪存储空间; 识别DFT方案和优先级之间的所有关系，并使存储单元将指示DFT方案和优先级之间的关系的信息存储到测试流数据库中; 以及根据DFT方案和优先级之间的关系按优先顺序排列DFT方案，使存储单元将DFT方案存储为测试流程，并使输出单元输出测试流程。

公开(公告)号：US20110131217A1

公开(公告)日：2011-06-02

申请号：US12958350

申请日：2010-12-01

申请人： Kazuhiko Iwasaki ,  Masayuki Arai ,  Kenichi Ichino

发明人： Kazuhiko Iwasaki ,  Masayuki Arai ,  Kenichi Ichino

IPC分类号： G06F17/30

CPC分类号： G01R31/2846

摘要： A program executed on a computer including storage, processing, output, and input units, the storage unit storing test-difficulty-calculation-elements-database, test-menu-database, and test-flow-database, for each test-menu-record, the program causing the processing unit to execute: calculating test-difficulty for each test-menu-record based on test-difficulty-calculation-formula by using at least one among pieces of information indicative of relationship with netlist, the number of package/test pins, expected operational clock frequency, process technology information, power consumption, and tester storage space; identifying all relationship between DFT scheme and priority, and causing the storage unit to store information indicative of the relationship between the DFT scheme and priority into the test-flow-database; and sorting the DFT scheme in an order of the priority based on the relationship between the DFT scheme and priority, causing the storage unit to store the DFT scheme as a test flow, and causing the output unit to output the test flow.

摘要翻译： 在包括存储，处理，输出和输入单元的计算机上执行的程序，存储单元存储测试难度计算单元数据库，测试菜单数据库和测试流程数据库， 记录，使得处理单元执行的程序：基于测试难度计算公式计算每个测试菜单记录的测试难度，通过使用指示与网表的关系的信息中的至少一个，包的数量 /测试引脚，预期的工作时钟频率，工艺技术信息，功耗和测试仪存储空间; 识别DFT方案和优先级之间的所有关系，并使存储单元将指示DFT方案和优先级之间的关系的信息存储到测试流数据库中; 以及根据DFT方案和优先级之间的关系按优先顺序排列DFT方案，使存储单元将DFT方案存储为测试流程，并使输出单元输出测试流程。

公开(公告)号：US08475054B2

公开(公告)日：2013-07-02

申请号：US12992835

申请日：2009-05-13

申请人： Akihiro Shimotsu ,  Masayuki Arai

发明人： Akihiro Shimotsu ,  Masayuki Arai

IPC分类号： G02B6/38

CPC分类号： H01R12/79 ,  G02B6/3817 ,  G02B6/4214 ,  G02B6/4292 ,  H01R12/714 ,  H01R12/88

摘要： An electric connector comprises a conductive terminal and a housing. The conductive terminal is provided with a terminal body portion, a soldering portion, to which an end portion of an electric wire is soldered, and a connection portion connected to a counterpart terminal. The housing is provided with a terminal receipt-hole, in which at least a portion of the terminal body portion is received, and a soldering portion accommodation-groove, in which at least a portion of the soldering portion is accommodated. The soldering portion accommodation-groove is provided with inner side walls, that extend along lateral ends of a soldering surface of the soldering portion, and a concave portion, which is formed in the inner side walls so that a portion of solder that is used for soldering of the end portion of the electric wire is able to come into the concave portion.

摘要翻译： 电连接器包括导电端子和壳体。 导电端子设置有端子主体部分，焊接端部的焊接部分和连接到对方端子的连接部分。 壳体设置有端子收容孔，终端主体部分的至少一部分被容纳在其中容纳有至少一部分焊接部的焊接部容纳槽。 焊接部容纳槽设置有沿着焊接部的焊接面的侧端延伸的内侧壁和形成在内侧壁中的凹部，使得用于 电线的端部的焊接能够进入凹部。

公开(公告)号：US08449202B2

公开(公告)日：2013-05-28

申请号：US12997707

申请日：2009-06-11

申请人： Akihiro Shimotsu ,  Masayuki Arai

发明人： Akihiro Shimotsu ,  Masayuki Arai

IPC分类号： G02B6/38 ,  H01R33/945

CPC分类号： G02B6/3883 ,  G02B6/3817 ,  G02B6/4214 ,  G02B6/4228 ,  G02B6/4246 ,  G02B6/4292 ,  G02B6/4416

摘要： A connector comprises a housing, a lever and a lock portion. The housing receives terminals. The lever, rotatably attached to the housing, is configured to be rotatable between a first position, where an initial stage of fitting to a counterpart connector is established, and a second position, where the fitting thereof is completed. The lock portion, capable of locking the lever at the second position, is slidably attached to a body portion of the lever, and configured to be slid between a lock position and a lock release position. The lever is provided with a positioning latch-portion configured to latch the lock portion. The positioning latch-portion is provided with a concave latch-portion and a convex latch-portion configured to be elastically displaced to be engaged in or disengaged from the concave latch-portion.

摘要翻译： 连接器包括壳体，杠杆和锁定部分。 房屋接收终端。 可旋转地附接到壳体的杠杆构造成可以在建立与配对连接器的初始装配阶段的第一位置和其中装配完成的第二位置之间旋转。 能够将杆锁定在第二位置的锁定部分可滑动地附接到杆的主体部分，并且构造成在锁定位置和锁定释放位置之间滑动。 杠杆设置有被配置为闩锁锁定部分的定位闩锁部分。 定位闩锁部分设置有凹形闩锁部分和凸形闩锁部分，该闩锁部分被构造成弹性位移以与凹形闩锁部分接合或脱离。

公开(公告)号：US20120183264A1

公开(公告)日：2012-07-19

申请号：US13384059

申请日：2010-07-13

申请人： Akihiro Shimotsu ,  Masayuki Arai

发明人： Akihiro Shimotsu ,  Masayuki Arai

IPC分类号： G02B6/36

CPC分类号： G02B6/4292 ,  G02B6/3885 ,  G02B6/4201 ,  G02B6/4214 ,  G02B6/426 ,  G02B6/4274 ,  G02B6/4281 ,  G02B6/4283 ,  G02B6/4293 ,  G02B6/43

摘要： An optical connector is disclosed. The optical connector includes a cable having formed therein an optical waveguide, a plug having the cable connected thereto, and a connector housing configured to mount thereon the plug. The cable is provided with a cable-side guide portion. The plug is provided with a plug housing which has a plug-side guide portion and is attached to the cable. The connector housing is provided with a connector-side guide portion. The plug-side guide portion is configured to be engaged with the cable-side guide portion to achieve a positioning of the cable and the plug housing and be engaged with the connector-side guide portion to achieve a positioning of the connector housing and the plug.

摘要翻译： 公开了一种光连接器。 光学连接器包括其中形成有光波导的电缆，具有连接到其上的电缆的插头以及配置成在其上安装插头的连接器壳体。 电缆设有电缆侧引导部。 插头设置有插头壳体，该插头壳体具有插头侧引导部分并且附接到电缆。 连接器壳体设置有连接器侧引导部。 插头侧引导部分被配置为与电缆侧引导部分接合以实现电缆和插头壳体的定位并且与连接器侧引导部分接合以实现连接器壳体和插头的定位 。

公开(公告)号：US20060291347A1

公开(公告)日：2006-12-28

申请号：US11439604

申请日：2006-05-24

申请人： Hisao Osabe ,  Masayuki Arai

发明人： Hisao Osabe ,  Masayuki Arai

IPC分类号： G11B20/00

CPC分类号： G11B20/1217 ,  G11B20/1262 ,  G11B2020/1297 ,  G11B2220/211 ,  G11B2220/235 ,  G11B2220/2541 ,  G11B2220/2562 ,  G11B2220/2579 ,  G11B2220/2583

摘要： An information processing apparatus for executing a process of recording data on a multilayer optical disk. The information processing apparatus includes: an encoding unit for encoding data to be written; a modulation unit for modulating the encoded data to generate a plurality of modulated data blocks corresponding to different recording formats; a pickup for sequentially writing the modulated data blocks in the different recording formats to different layers of the optical disk; and a control unit for controlling the writing of the modulated data blocks in the different recording formats so that writing processing per unit of modulated data is completed within processing time per unit of data encoded by the encoding unit.

摘要翻译： 一种用于执行在多层光盘上记录数据的处理的信息处理装置。 该信息处理装置包括：编码单元，用于对待写入的数据进行编码; 调制单元，用于调制编码数据以产生对应于不同记录格式的多个调制数据块; 用于将不同记录格式的调制数据块顺序地写入光盘的不同层的拾取器; 以及控制单元，用于控制不同记录格式的调制数据块的写入，使得每单位调制数据的写入处理在由编码单元编码的每单位数据的处理时间内完成。

公开(公告)号：US06778476B2

公开(公告)日：2004-08-17

申请号：US10145114

申请日：2002-05-15

申请人： Yoshinori Tsuboi ,  Masayuki Arai

发明人： Yoshinori Tsuboi ,  Masayuki Arai

IPC分类号： G11B700

CPC分类号： G11B27/24 ,  G11B7/0053 ,  G11B7/00718 ,  G11B7/00745 ,  G11B20/10 ,  G11B27/19 ,  G11B2220/2525 ,  G11B2220/2562

摘要： An information playback apparatus is disclosed which can play back information with a high degree of accuracy. The information playback apparatus plays back the addresses from a recording medium on which a land address and a groove address are recorded at positions displaced from each other. The information playback apparatus includes an AM detection circuit for detecting an AM read out from the recording medium to produce an AM detection pulse signal, a masking signal production circuit and an AND circuit for removing, when a pickup scans the land, an AM detection pulse produced while the pickup passes the land adjacent an area in which the groove address is recorded but removing, when the pickup scans the groove, an AM detection pulse produced while the pickup passes the groove adjacent an area in which the land address is recorded to produce a synchronism detection signal, and an address data decoding circuit for decoding the information in response to the synchronism detection signal to produce address data.

摘要翻译： 公开了可以高精度地回放信息的信息重放装置。 信息重放装置从其中记录有相互移位的位置的记录介质上回放地址。 信息重放装置包括用于检测从记录介质读出的AM以产生AM检测脉冲信号的AM检测电路，掩蔽信号产生电路和AND电路，用于当拾取器扫描岸台时，去除AM检测脉冲 当拾取器通过相邻于其中记录凹槽地址的区域的区域时，当拾取器扫描凹槽时，移除在拾取器通过与记录该地址的区域相邻的凹槽产生的AM检测脉冲 同步检测信号和地址数据解码电路，用于响应于同步检测信号对信息进行解码以产生地址数据。