公开(公告)号：US4683533A

公开(公告)日：1987-07-28

申请号：US664771

申请日：1984-10-25

申请人： Kenichi Shiozaki ,  Kanji Kubo

发明人： Kenichi Shiozaki ,  Kanji Kubo

IPC分类号： G06F12/08 ,  G06F13/18 ,  G06F13/00 ,  G11C29/00

CPC分类号： G06F13/18 ,  G06F12/0822

摘要： A storage control system controls the update operations on two buffer address arrays in a data processing system in which a plurality of processors are connected to a shared storage, at least one of the processors having a buffer storage. The first buffer address array is the directory of buffer storage. The second buffer address array contains the same data as that of the first buffer address array. The storage control system updates first the content of the second buffer address array then that of the first buffer address array in response to a block transfer to the buffer storage of the own processor and a store operation conducted by other processor on the shared storage. The storage control system permits to accept a new access request occurred in the own processor on condition that a block transfer to the own processor is finished and that the first buffer address array is updated in association with the block transfer.

摘要翻译： 存储控制系统控制其中多个处理器连接到共享存储器的数据处理系统中的两个缓冲器地址阵列上的更新操作，至少一个处理器具有缓冲存储器。 第一个缓冲区地址数组是缓冲存储的目录。 第二缓冲地址数组包含与第一缓冲地址数组相同的数据。 存储控制系统响应于对自身处理器的缓冲存储器的块传送和在其他处理器对共享存储器进行的存储操作，首先更新第二缓冲器地址阵列的内容以及第一缓冲器地址阵列的内容。 存储控制系统允许在完成对自己的处理器的块传送并且与块传送相关联地更新第一缓冲器地址阵列的情况下接受在自己的处理器中发生的新的访问请求。

公开(公告)号：US4658356A

公开(公告)日：1987-04-14

申请号：US553235

申请日：1983-11-18

申请人： Kenichi Shiozaki ,  Makoto Kishi ,  Tomoatsu Yanagita ,  Kanji Kubo

发明人： Kenichi Shiozaki ,  Makoto Kishi ,  Tomoatsu Yanagita ,  Kanji Kubo

IPC分类号： G06F12/10 ,  G06F12/08 ,  G06F12/14 ,  G06F13/00 ,  G06F13/14

CPC分类号： G06F12/0804 ,  G06F12/1475 ,  G06F13/00

摘要： Change bits are provided in correspondence with storage information units (blocks or pages) of a storage, and indicate whether or not a "store" operation has been performed into the corresponding storage information units. The change bits are retained in a first retention device in correspondence with the storage information units, and a copy of the change bits in the first retention device is retained in a second retention device. When the store operation is performed to effect a storing of data into the storage, a control device refers to the change bit retained by the second retention device and controls updating of the change bit of the first retention device in accordance with the indication of the change bit referred to.

摘要翻译： 与存储器的存储信息单元（块或页）相对应地提供更改位，并且指示是否已经对相应的存储信息单元执行“存储”操作。 更改位与存储信息单元对应地保留在第一保持装置中，并且第一保持装置中的更改位的副本保留在第二保持装置中。 当执行存储操作以将数据存储到存储器中时，控制装置参考由第二保持装置保持的更改位，并且根据变化的指示控制第一保持装置的更改位的更新 位参考。

公开(公告)号：US4670836A

公开(公告)日：1987-06-02

申请号：US618257

申请日：1984-06-07

申请人： Kanji Kubo ,  Kenichi Shiozaki

发明人： Kanji Kubo ,  Kenichi Shiozaki

IPC分类号： G06F9/38 ,  G06F12/02

CPC分类号： G06F9/3834

摘要： In order to guarantee the instruction execution sequence in a pipeline control data processing system, the present overlap detector device detects whether or not the operands overlap each other in access width units by comparing the store address specified by a store instruction with the fetch address contained in a fetch instruction following the store instruction. Moreover, the overlap detector device detects whether or not an overlap occurs in an area of the access width based on the store mark, the address in the access width unit stored in the fetch address, and the fetch data length. The overlap detector device detects the presence or absence of an overlap according to the results of operations for detecting these two overlap conditions.

摘要翻译： 为了保证流水线控制数据处理系统中的指令执行顺序，本重叠检测装置通过将由存储指令指定的存储地址与包含在存储指令中的获取地址进行比较来检测操作数是否以访问宽度单位彼此重叠 存储指令之后的取指令。 此外，重叠检测装置基于存储标记，存储在取出地址中的访问宽度单元中的地址和取出数据长度来检测在访问宽度的区域中是否发生重叠。 重叠检测装置根据用于检测这两个重叠条件的操作结果来检测是否存在重叠。