公开(公告)号：US06714596B1

公开(公告)日：2004-03-30

申请号：US09582228

申请日：2000-07-21

申请人： Kenichi Shiraishi ,  Akihiro Horii ,  Soichi Shinjo ,  Shoji Matsuda ,  Ryuichi Okazaki

发明人： Kenichi Shiraishi ,  Akihiro Horii ,  Soichi Shinjo ,  Shoji Matsuda ,  Ryuichi Okazaki

IPC分类号： H04L2302

CPC分类号： H04L1/0052 ,  H04L1/0054 ,  H04L1/006 ,  H04L27/2332 ,  H04L2027/0032 ,  H04L2027/0057

摘要： A BS digital broadcast receiver having no 8PSK-demapper and a less number of delay circuits for Trellis encoding. A QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal is Viterbi-decoded by a Viterbi-decoder 6. An output of the Viterbi-decoder is convolution-reencoded by a convolution encoder 7. Upper four bits of phase error data are searched from a phase error table 31 for carrier reproduction in accordance with a phase difference between 0 degree and a phase of a phase error detection reception signal point position. The upper four bits are delayed by delay circuits 81 to 84 by a total sum of a time taken to Viterbi-decode and a time taken to convolution-encode. The delayed outputs are demapped by a demapped value conversion circuit 9. A code TCD2 determined from the demapped output and convolution encode output is output as an MSB of a Trellis 8PSK decode output from an MSB code judging/error detecting circuit 10.

摘要翻译： 没有8PSK解映射器的BS数字广播接收机和用于网格编码的较少数量的延迟电路。 基于绝对相位基带解调信号的接收信号点位置的QPSK基带信号由维特比解码器6进行维特比解码。维特比解码器的输出由卷积编码器7进行卷积重新编码。高四位 根据0度与相位误差检测接收信号点位置的相位之间的相位差，从用于载波再现的相位误差表31中搜索相位误差数据。 延迟电路81至84通过维特比解码所花费的时间和对卷积编码所花费的时间的总和来延迟高四位。 延迟的输出被去映射值转换电路9解映射。从解映射的输出和卷积编码输出确定的代码TCD2作为从MSB代码判断/错误检测电路10的格状8PSK解码输出的MSB输出。

公开(公告)号：US06700940B1

公开(公告)日：2004-03-02

申请号：US09581212

申请日：2000-08-15

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Tomohiro Saito ,  Fumiaki Minematsu ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Tomohiro Saito ,  Fumiaki Minematsu ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

IPC分类号： H04B1700

CPC分类号： H04L27/2273

摘要： A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit (4), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180°, which are included in a carrier reproduction phase difference detecting circuit (8), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit (10) so that the phase obtained from the signal point position coincides with the phase convergence point.

摘要翻译： 提供即使在以低C / N值进行接收的情况下也能够执行稳定的载波再现的载波再现电路。 利用帧同步定时电路（4）检测解调的已知模式接收信号的接收相位，并且基于检测到的接收相位，具有一个收敛点的绝对相位的相位差表或者具有一个收敛点的相位差表 选择包含在载波再现相位差检测电路（8）中的从绝对相位旋转180°的相位，并且从所选择的相位差表中选择基于从信号点获得的相位之间的相位差的输出 获得接收信号和相位收敛点的位置，从而通过经由AFC电路（10）经历再现的载波频率控制来实现载波再现，使得从信号点位置获得的相位与相位收敛点一致。

公开(公告)号：US06678336B1

公开(公告)日：2004-01-13

申请号：US09554669

申请日：2000-08-09

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

IPC分类号： H04L2706

CPC分类号： H04L27/2332 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0081 ,  H04L2027/0095

摘要： A hierarchical transmission digital demodulator capable of stable sync capture and stable demodulation through setting of a demodulation operation in accordance with a reception C/N value. A CNR measuring circuit receives a demodulation output from an arithmetic circuit and measures a reception C/N value. During a period until sync is captured, a carrier is reproduced in accordance with the demodulation output that a modulated wave in a header section and a modulated wave of burst symbol signal. After sync is captured, at an intermediate C/N value the carrier is reproduced in accordance with the demodulation output of the header section, burst symbol signal and QPSK signal and in accordance with output from a logical gate circuit, and at high and low C/N values the carrier is reproduced by setting high a carrier reproduction loop gain of a gain control circuit in accordance with a signal from the logical gate circuit.

摘要翻译： 一种能够通过根据接收C / N值设置解调操作来稳定同步捕获和稳定解调的分级发送数字解调器。 CNR测量电路从运算电路接收解调输出并测量接收C / N值。 在捕获同步之前的一段时间内，根据解调输出再现载波，以便在报头部分中的调制波和突发符号信号的调制波。 在捕获同步之后，以中间C / N值，根据标题部分的解调输出，突发符号信号和QPSK信号，并根据逻辑门电路的输出，以及在高和低C / N值通过根据来自逻辑门​​电路的信号设置增益控制电路的载波再生环路增益来重放载波。

公开(公告)号：US06639951B1

公开(公告)日：2003-10-28

申请号：US09554689

申请日：2000-05-18

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Tomohiro Saito ,  Fumiaki Minematsu ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Tomohiro Saito ,  Fumiaki Minematsu ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

IPC分类号： H04L2714

CPC分类号： H04L27/2332 ,  H04L7/04 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0095

摘要： A digital demodulator that eliminates the need for an absolute phase circuit is provided. In a digital demodulator for a digital broadcasting receiver that receives digital time-division multiplexed signals of different types of modulation, the demodulated baseband signal is selectively inverted by an inverter (7) according to an inversion command signal “0” or “1” that is output from an inversion decision circuit (6) depending on a BPSK signal of a known pattern. A phase error detector (8) for carrier reproduction determines the phase error voltage based on the phase difference between the absolute phase and the phase of the signal point of the demodulated baseband signal output from the inverter (7). The phase error voltage is passed through a carrier filter (9), including a low-pass filter, to control the carrier frequency so that carrier reproduction can be carried out with the phase at the signal point being coincident with the point of phase convergence.

摘要翻译： 提供了一种无需绝对相位电路的数字解调器。 在用于数字广播接收机的数字解调器中，接收不同类型调制的数字时分多路复用信号，根据反相器（7）根据反相指令信号“0”或“1”选择性地将解调的基带信号反相， 根据已知图案的BPSK信号从反转判定电路（6）输出。 用于载波再现的相位误差检测器（8）基于从逆变器（7）输出的解调的基带信号的信号点的绝对相位和相位之间的相位差来确定相位误差电压。 相位误差电压通过包括低通滤波器的载波滤波器（9），以控制载波频率，使得载波再现可以在信号点处的相位与相位收敛点一致。

公开(公告)号：US07529321B1

公开(公告)日：2009-05-05

申请号：US09805766

申请日：1999-09-17

申请人： Kenichi Shiraishi ,  Shoichi Suzuki ,  Akihiro Horii ,  Shoji Matsuda ,  Takahiro Wada

发明人： Kenichi Shiraishi ,  Shoichi Suzuki ,  Akihiro Horii ,  Shoji Matsuda ,  Takahiro Wada

IPC分类号： H04L27/22

CPC分类号： H04H20/74 ,  H04L1/20 ,  H04L27/2273 ,  H04L27/2332 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0081

摘要： A digital satellite broadcast receiver capable of an optimum signal reception even when an arbitrary outdoor unit is connected. Please noise characteristics of an outdoor unit connected to a digital satellite broadcast receiver when receiving a burst symbol is estimated based on a bit error rate of an 8PSK modulation signal determined by a trellis decoder (7) when a CNR measured by a CNR measurement circuit (5) is equal to a preset value, and, based on the estimated phase noise characteristics of the outdoor unit, a filter factor of a loop filter (9) inserted into a carrier regenerative loop is set.

摘要翻译： 即使连接任意的室外机也能够进行最佳的信号接收的数字卫星广播接收机。 当接收到突发符号时，连接到数字卫星广播接收机的室外单元的噪声特性基于由CNR测量电路（CNR）测量的CNR由网格解码器（7）确定的8PSK调制信号的误比特率 5）等于预设值，并且基于所估计的室外单元的相位噪声特性，设置插入到载波再生回路中的环路滤波器（9）的滤波器因子。

公开(公告)号：US07283569B2

公开(公告)日：2007-10-16

申请号：US10168148

申请日：2000-12-19

申请人： Hiroshi Okamura ,  Tomokazu Nakajima ,  Takanori Fujii ,  Susumu Nishijima ,  Masaki Miyamoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

发明人： Hiroshi Okamura ,  Tomokazu Nakajima ,  Takanori Fujii ,  Susumu Nishijima ,  Masaki Miyamoto ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

IPC分类号： H04J3/06

CPC分类号： H04L1/06 ,  H04B7/18523 ,  H04B7/18534 ,  H04B7/2125 ,  H04H20/26 ,  H04H20/74

摘要： A site diversity method, a digital satellite broadcast receiving method and a digital satellite broadcast receiver are provided which can make a difference of data output timing between a main station and a subsidiary station at the time of site exchange as small as possible and can perform re-synchronization as soon as possible. In the site diversity method for digital satellite broadcast, when a site exchange execution designation signal is received, the site is exchanged during a period of a TMCC information field of a predetermined specific frame of a super frame determined when the execution designation signal is received. On the receiver side, information of broadcast is continuously received by detecting a TMCC information field in a specific frame during a period of which field the site was exchanged and by establishing re-synchronization by using a super frame sync pattern W2 or W3 after the detected TMCC information field.

摘要翻译： 提供一种站点分集方法，数字卫星广播接收方法和数字卫星广播接收机，其可以在站点交换时使主站和辅助站之间的数据输出定时的差异尽可能小，并且可以执行re - 尽快同步。 在数字卫星广播的站点分集方法中，当接收到站点交换执行指定信号时，在接收到执行指定信号时确定的超帧的预定特定帧的TMCC信息字段的周期期间交换站点。 在接收机侧，通过在交换场所的时段期间检测特定帧中的TMCC信息字段并且通过使用超帧同步模式W 2或W 3之后建立再同步来连续接收广播信息 检测到的TMCC信息字段。

公开(公告)号：US07221719B2

公开(公告)日：2007-05-22

申请号：US10031085

申请日：2001-05-17

申请人： Kenichi Shiraishi ,  Shoji Matsuda ,  Akihiro Horii

发明人： Kenichi Shiraishi ,  Shoji Matsuda ,  Akihiro Horii

IPC分类号： H04L27/14

CPC分类号： H04L27/2273 ,  H04L27/0012 ,  H04L2027/0053 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0069

摘要： An improved apparatus for receiving BS digital broadcast is disclosed. The apparatus for receiving BS digital broadcast of the present invention has first to third filters and a selective complex calculator circuit.Each of the first to third filters 18 to 20 identifies the modulation technique applied to the received signal, by the modulation identification signals A0, A1 received from a timing generator circuit 25, and filters a phase error signal PED according to the identified modulation technique. The selective complex calculator circuit 21 shifts the phase of a signal point indicated by an I signal ADI1 and a Q signal ADQ1 absolute-phased by an absolute-phasing section 14, by a phase corresponding to the phase error signal filtered by the first to third filters 18 to 20. At this moment, the selective complex calculator circuit 21 selects the phase error signal corresponding to the modulation technique identified from the modulation identification signals A0, A1 received from the timing generator circuit 25. Consequently, in the burst receiving, it is possible to reduce the effect on the error rate because of the signal noise of the ODU to a degree equal to that in the continuous receiving.

摘要翻译： 公开了一种用于接收BS数字广播的改进的装置。 本发明的用于接收BS数字广播的装置具有第一至第三滤波器和选择性复合计算器电路。 第一至第三滤波器18至20中的每一个通过从定时发生器电路25接收的调制识别信号A 0，A 1识别应用于接收信号的调制技术，并根据所识别的调制对相位误差信号PED进行滤波 技术。 选择复合计算器电路21将由由绝对定相部分14绝对相位的I信号ADI 1和Q信号ADQ 1指示的信号点的相位移位相应于由第一 到第三过滤器18至20。 此时，选择性复数计算器电路21选择与从定时发生器电路25接收的调制识别信号A 0，A 1识别的调制技术相对应的相位误差信号。 因此，在脉冲串接收中，由于ODU的信号噪声等于连续接收的信号噪声，可以降低对误码率的影响。

公开(公告)号：US07079597B1

公开(公告)日：2006-07-18

申请号：US10049808

申请日：2000-10-02

申请人： Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

发明人： Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

IPC分类号： H04L27/16 ,  H04L7/00 ,  H04J3/06

CPC分类号： H04L7/042 ,  H04L27/22 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0065 ,  H04L2027/0067

摘要： Frame synchronization is quickly established to acquire an RF channel in a short time. Numerically controlled oscillators 1-1 to 1-3, complex calculation circuits 2-1 to 2-3, band limit filters 3-1 to 3-3, a selector 7, a phase error detection circuit 9, a loop filter 10, and an AFC circuit 11 compose a carrier regeneration loop for removing the frequency error of the carrier included in an in-phase component I and a quadrant component Q of the baseband signal input to the complex calculation circuits 2-1 to 2-3. A timing generator 6 detects which of frame synchronization pattern detection circuits 5-1 to 5-3 has detected a frame synchronization pattern, provides the selector 7 with a selection signal corresponding to the decision result, and sends a switch signal to the AFC circuit 11. Thereafter, the carrier for removing the frequency error included in the baseband signal is regenerated to acquire an RF channel in a short time.

摘要翻译： 快速建立帧同步，以在短时间内获取RF信道。 数字控制振荡器1-1-1-3，复数计算电路2-1-2-3，频带限制滤波器3-1至3-3，选择器7，相位误差检测电路9，环路滤波器10和 AFC电路11构成用于去除包括在同相分量I中的载波的频率误差的载波再生回路和输入到复数计算电路2-1至2-3的基带信号的象限分量Q。 定时发生器6检测哪个帧同步模式检测电路5-1至5-3已经检测到帧同步模式，向选择器7提供与该决定结果相对应的选择信号，并向AFC电路11发送开关信号 。 此后，重新生成用于消除基带信号中包括的频率误差的载波，以在短时间内获取RF信道。

公开(公告)号：US06813321B1

公开(公告)日：2004-11-02

申请号：US09582229

申请日：2000-07-21

申请人： Hisakazu Katoh ,  Akinori Hashimoto ,  Yuichi Iwadate ,  Kazuhiko Shibuya ,  Fumiaki Minematsu ,  Shigeyuki Itoh ,  Tomohiro Saito ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

发明人： Hisakazu Katoh ,  Akinori Hashimoto ,  Yuichi Iwadate ,  Kazuhiko Shibuya ,  Fumiaki Minematsu ,  Shigeyuki Itoh ,  Tomohiro Saito ,  Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda ,  Soichi Shinjo

IPC分类号： H03D322

CPC分类号： H04L27/2273 ,  H04L7/042 ,  H04L27/0014 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0077 ,  H04L2027/0095

摘要： A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit 6 generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit 7 has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter 8 according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit 6, the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.

摘要翻译： 提供了不需要绝对定相电路的数字解调器。 已知模式BPSK信号发生电路6与接收的数字调制波中的已知模式BPSK信号同步地产生与接收的数字调制波中已知模式BPSK信号相同的已知模式BPSK信号，载波再现 相位误差检测电路7具有相位误差表，其中解调基带信号的信号点位置中的参考相位之一成为会聚点，相位误差电压对应于从信号点位置确定的相位之间的相位误差 通过根据从已知模式BPSK信号发生电路6输出的已知模式BPSK信号启用控制载波再现环路滤波器8，发送解调基带信号和相位收敛点，平滑相位误差电压 并且在根据平滑输出控制再现载波的频率的同时执行载波再现，使得si中的相位 点位置与相位收敛点一致。

公开(公告)号：US06993096B1

公开(公告)日：2006-01-31

申请号：US09959267

申请日：2000-04-04

申请人： Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

发明人： Kenichi Shiraishi ,  Akihiro Horii ,  Shoji Matsuda

IPC分类号： H03D3/22 ,  H04L27/22

CPC分类号： H04L27/2272 ,  H04L27/22 ,  H04L2027/003 ,  H04L2027/0057 ,  H04L2027/0073 ,  H04L2027/0079 ,  H04L2027/0095 ,  H04N5/4401 ,  H04N5/455 ,  H04N21/426 ,  H04N21/4382 ,  H04N21/6143

摘要： A BS digital broadcasting receiver which eliminates the uncertainty of an ODU's phase noise-dependent switching point when switching a receiving system. The receiver is provided with a demodulator circuit (6A) having a carrier regenerating circuit (19A) based on demodulation data in a BPSK modulation section, and with a demodulator circuit (6B) having a carrier regenerating circuit (19B) based on demodulation data in each time-division modulation section, wherein, when a lock for carriers regenerated by the carrier regenerating circuit (19A) is maintained and carriers regenerated by the carrier regenerating circuit (19B) is locked, demodulation data, in the BPSK demodulation section and a QPSK demodulation section, output from the demodulator circuit (6A) and 8-PSK-modulated demodulation data output from the demodulator circuit (6B) are selected by a selector (7) for outputting.

摘要翻译： 一种BS数字广播接收机，用于在切换接收系统时消除ODU相位噪声相关切换点的不确定性。 接收机具有基于BPSK调制部分中的解调数据的具有载波再生电路（19A）的解调器电路（6A），并且具有基于载波再生电路（19B）的解调器电路（6B） 在每个时分调制部分中的解调数据上，其中当保持由载波再生电路（19A）再生的载波的锁定并且由载波再生电路（19B）再生的载波被锁定时，解调数据在 由解调器电路（6A）输出的BPSK解调部分和QPSK解调部分和从解调器电路（6B）输出的8-PSK调制解调数据由选择器（7）选择输出。