公开(公告)号：US5414703A

公开(公告)日：1995-05-09

申请号：US169553

申请日：1993-12-20

申请人： Kenji Sakaue ,  Yasuro Shobatake ,  Masahiko Motoyama ,  Yoshinari Kumaki

发明人： Kenji Sakaue ,  Yasuro Shobatake ,  Masahiko Motoyama ,  Yoshinari Kumaki

IPC分类号： H04Q3/52 ,  H04J3/06 ,  H04L12/931 ,  H04J3/14

CPC分类号： H04J3/0632 ,  H04L12/5601 ,  H04L49/106 ,  H04L49/1553 ,  H04L49/256 ,  H04L2012/5681

摘要： A unit cell switch includes a plurality of input communication routes and output communication routes for transferring data cells therebetween, a plurality of first conversion devices for converting each cell given from these input communication routes into a desired form, a plurality of second conversion devices for converting each data given from the first conversion devices into a suitable form and transferring the resultant data to one of these output communication routes. Cell storing devices respectively receive and temporarily store cells transferred from corresponding first conversion devices based on address information given to the cells. A control device holds and controls route and address information on cells to be stored in the cell storing devices as unitary data, and decides a write address of each cell storing device to which a cell is given from the corresponding first cell conversion device and a read address of each cell storing device from which a cell is outputted to a cell switch device based on the route and address information. A cell switch device introduces cells to desired second cell conversion devices from corresponding cell storing devices under control of the transfer control device.

摘要翻译： 单元单元开关包括多个输入通信路径和用于在其间传送数据单元的输出通信路由，用于将从这些输入通信路由给出的每个单元转换为期望形式的多个第一转换设备，用于转换的多个第二转换设备 每个数据从第一转换装置给出合适的形式，并将结果数据传送到这些输出通信路线之一。 基于给予小区的地址信息，小区存储设备分别接收并临时存储从相应的第一转换设备传送的小区。 控制装置将要存储在信元存储装置中的信元的路由和地址信息保存并控制为单位数据，并且从相应的第一小区转换装置确定给予小区的每个信元存储装置的写入地址 基于路由和地址信息将小区输出到小区交换设备的每个小区存储设备的地址。 小区交换设备在传输控制设备的控制下，将小区引入来自相应的小区存储设备的期望的第二小区转换设备。

公开(公告)号：US5940377A

公开(公告)日：1999-08-17

申请号：US773791

申请日：1996-12-18

申请人： Kenji Sakaue ,  Masahiko Motoyama

发明人： Kenji Sakaue ,  Masahiko Motoyama

IPC分类号： H04L12/54 ,  H04L12/935 ,  H04L12/939 ,  H04J3/16

CPC分类号： H04L49/30 ,  H04L12/5601 ,  H04L49/3009 ,  H04L49/3027 ,  H04L49/555

摘要： An ATM switch having multiple input and output ports is provided. The ATM switch receives ATM cells through the input ports and outputs the ATM cells through one of the output ports in accordance with output port information included in the ATM cells. An output buffer is also provided for each of the output ports to store ATM cells to be output through the output port. A cell counter is provided for each of the output buffers to count the number of ATM cells being stored in the output buffer. Additionally, the ATM switch includes counter verification circuitry for determining whether the cell counters are correctly counting the number of ATM cells stored in the output buffers. In one preferred embodiment, the counter verification circuitry includes a global cell counter that counts the total number of ATM cells being stored in all of the output buffers, an accumulator that determines the total number of ATM cells counted by the cell counters, and a comparator for comparing the accumulated count value with the global count value. Thus, the proper operation of the cell counters can be verified. This minimizes the possibility of improper operation due to a malfunction, even when the ATM switch is operated continuously for a long time period.

摘要翻译： 提供具有多个输入和输出端口的ATM交换机。 ATM交换机通过输入端口接收ATM信元，并根据ATM信元中包含的输出端口信息通过其中一个输出端口输出ATM信元。 还为每个输出端口提供输出缓冲器以存储要通过输出端口输出的ATM信元。 为每个输出缓冲器提供单元计数器以对存储在输出缓冲器中的ATM单元的数量进行计数。 此外，ATM交换机包括用于确定小区计数器是否正确地计数存储在输出缓冲器中的ATM信元的数量的计数器验证电路。 在一个优选实施例中，计数器验证电路包括一个全局单元计数器，用于对存储在所有输出缓冲器中的ATM单元的总数进行计数，累加器确定由单元计数器计数的ATM单元的总数，以及比较器 用于将累积计数值与全局计数值进行比较。 因此，可以验证单元计数器的适当操作。 这样即使在ATM开关长时间连续运行的情况下，由于故障也可能导致操作不当。

公开(公告)号：US20130267110A1

公开(公告)日：2013-10-10

申请号：US13880836

申请日：2011-10-14

申请人： Motomu Kajiura ,  Naotaka Sasame ,  Masahiko Motoyama

发明人： Motomu Kajiura ,  Naotaka Sasame ,  Masahiko Motoyama

IPC分类号： H01R12/72

CPC分类号： H01R12/774 ,  H01R12/72 ,  H01R12/79 ,  H01R12/88 ,  H01R13/6471 ,  H01R13/6477 ,  H01R13/6597

摘要： A high speed flexible printed circuit (FPC) connector includes a housing with ground and signal contact terminal pairs arranged in the housing in a staggered manner along a lateral direction. The housing has a cavity for receiving an FPC board therein. Each ground contact terminal has an upper arm positioned adjacent to a top wall of the cavity and a lower arm positioned adjacent to a bottom wall of the cavity. Each signal contact terminal has only a lower arm positioned adjacent to the bottom wall of the cavity. Signal contact terminals with the only lower arm provide the connector with better signal integrity. An actuator is coupled to the housing for fixing the FPC board in the cavity to establish electrical connections. The actuator has recesses corresponding to the positions of the signal pairs to provide a dielectric constant different from that of the other parts of the actuator.

公开(公告)号：US20100257373A1

公开(公告)日：2010-10-07

申请号：US12715558

申请日：2010-03-02

申请人： Masahiko Motoyama

发明人： Masahiko Motoyama

IPC分类号： G06F12/14

CPC分类号： G06F21/755

摘要： A cryptographic processor has a first cryptographic processing circuit configured to perform first cryptographic processing on input first data, and a second cryptographic processing circuit configured to perform second cryptographic processing different from the first cryptographic processing on input second data by using a processing result from the first cryptographic processing circuit as mask data.

摘要翻译： 密码处理器具有：第一加密处理电路，被配置为对输入的第一数据执行第一密码处理;以及第二密码处理电路，被配置为通过使用来自所述第一数据的处理结果，对与输入的第二数据进行的第一密码处理不同的第二密码处理 密码处理电路作为掩码数据。

公开(公告)号：US07194090B2

公开(公告)日：2007-03-20

申请号：US09902696

申请日：2001-07-12

申请人： Hirofumi Muratani ,  Masahiko Motoyama ,  Kenji Ohkuma ,  Fumihiko Sano ,  Shinichi Kawamura

发明人： Hirofumi Muratani ,  Masahiko Motoyama ,  Kenji Ohkuma ,  Fumihiko Sano ,  Shinichi Kawamura

IPC分类号： H04K1/00 ,  H04L9/00

CPC分类号： H04L9/002 ,  H04L9/0618 ,  H04L2209/08 ,  H04L2209/125 ,  H04L2209/20 ,  H04L2209/24

摘要： Expanded key schedule circuit for common key encryption system in which expanded keys are used in a predetermined order in data randomizing process for encryption and in a reversed order in data randomizing process for decryption, comprises round processing circuits connected in series. The round processing circuits subject the common key or sub key of a previous stage to a round function to output a sub key. The sub key of the last stage is equal to the common key. The expanded keys are generated from the sub keys.

摘要翻译： 用于通用密钥加密系统的扩展密钥调度电路，其中扩展密钥以用于加密的数据随机化处理中的预定顺序以及用于解密的数据随机化处理中的相反顺序使用，包括串联连接的圆形处理电路。 圆处理电路将前一级的公共密钥或子密钥实施为循环函数以输出子密钥。 最后一级的子键等于公共密钥。 扩展的密钥是从子密钥生成的。

公开(公告)号：US5612952A

公开(公告)日：1997-03-18

申请号：US308794

申请日：1994-09-19

申请人： Masahiko Motoyama

发明人： Masahiko Motoyama

IPC分类号： H04L12/56 ,  H04J3/02

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/3081 ,  H04L49/309 ,  H04L2012/5651

摘要： A packet switch has a buffer memory for storing data obtained from data packets having routing tags input from a plurality of different input ports. Plural routing tag registers store the respective routing tags in the order of input. Plural address information registers respectively corresponding to the plural routing tag registers store address information representative of a buffer memory storage region where data corresponding to the routing tags are stored. A controller searches the routing tag registers in the order of their input. A reading is made of address information stored in the address information registers corresponding to routing tags for a special output port. Data stored in the storage region of the buffer memory indicated by the address information is output to the special output port. After the routing tag registers and the address information registers corresponding to the data have been output to the output port, contents of the routing tag registers and the address information registers are shifted to the next routing tag registers and address information registers in order.

摘要翻译： 分组交换机具有缓冲存储器，用于存储从具有从多个不同输入端口输入的路由标签的数据分组获得的数据。 多个路由标签寄存器按照输入顺序存储各个路由标签。 分别对应于多个路由标签寄存器的多个地址信息寄存器存储表示存储对应于路由标签的数据的缓冲存储器存储区域的地址信息。 控制器按照输入顺序搜索路由标签寄存器。 读取存储在与专用输出端口的路由标签相对应的地址信息寄存器中的地址信息。 存储在由地址信息指示的缓冲存储器的存储区域中的数据被输出到特殊输出端口。 在将路由标签寄存器和对应于数据的地址信息寄存器输出到输出端口之后，路由标签寄存器和地址信息寄存器的内容按顺序移位到下一个路由标签寄存器和地址信息寄存器。

公开(公告)号：US08155317B2

公开(公告)日：2012-04-10

申请号：US11934345

申请日：2007-11-02

申请人： Masahiko Motoyama

发明人： Masahiko Motoyama

IPC分类号： H04K1/02

CPC分类号： H04L9/0625 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12

摘要： An encryption processing circuit includes: a decoder configured to convert a binary input data used for predetermined encryption computing into a first plurality of bit data of a constant hamming weight independently of a hamming weight of the input data; a wiring network configured to receive the first plurality of bit data converted by the decoder, the wiring network further configured, for the purpose of the predetermined encryption computing, to change a bit pattern of the received first plurality of bit data by replacing bit positions of the first plurality of bit data, and to generate a second plurality of bit data; and an encoder configured to convert the second plurality of bit data generated in the wiring network into a binary output data.

摘要翻译： 加密处理电路包括：解码器，被配置为独立于输入数据的汉明权重将用于预定加密计算的二进制输入数据转换成恒定汉明权重的第一多个比特数据; 配置为接收由解码器转换的第一多个比特数据的布线网络，为了预定的加密计算，进一步配置的布线网络通过将所接收的第一多个比特数据的比特位置 所述第一多个比特数据，并且生成第二多个比特数据; 以及编码器，被配置为将在所述布线网络中生成的所述第二多个位数据转换为二进制输出数据。

公开(公告)号：US20110296198A1

公开(公告)日：2011-12-01

申请号：US13033671

申请日：2011-02-24

申请人： Masahiko Motoyama

发明人： Masahiko Motoyama

IPC分类号： H04L9/00

CPC分类号： G06F21/602 ,  H04L9/003 ,  H04L9/0625 ,  H04L9/0631 ,  H04L2209/08

摘要： A cryptographic processing apparatus according to embodiments includes a cryptographic operation processing section that can execute cryptographic processor of encryption operation and decryption operation, and a control section. The control section controls the execution of the cryptographic operation processing section such that a first operation for converting a first value, which is input data to be subjected to cryptographic processor, or intermediate data during cryptographic processor, into a second value, and a second operation for converting the second value into the first value are performed successively at least one time.

摘要翻译： 根据实施例的加密处理装置包括可执行加密操作和解密操作的加密处理器的加密操作处理部分和控制部分。 控制部分控制密码操作处理部分的执行，使得用于将作为密码处理器的输入数据的第一值或密码处理器期间的中间数据转换为第二值的第一操作和第二操作 用于将第二值转换为第一值的步骤至少连续执行一次。

公开(公告)号：US07583207B2

公开(公告)日：2009-09-01

申请号：US11872387

申请日：2007-10-15

申请人： Masahiko Motoyama

发明人： Masahiko Motoyama

IPC分类号： H03M7/00

CPC分类号： H03K19/0008 ,  H04L2209/12

摘要： A logic circuit that executes a prescribed arithmetic processing includes a decoder that converts one or more binary input data into a first plurality of bit data of a constant hamming weight regardless of a hamming weight of the input data, an interconnect network that is connected to the decoder, changes a bit pattern of the first plurality of bit data and generates a second plurality of bit data, according to receiving the first plurality of bit data converted according to the decoder, and substituting a bit position of the received first plurality of bit data for the purpose of the prescribed arithmetic operation, and an encoder connected to the interconnect network and converts the second plurality of bit data generated in the interconnect network into one or more binary output data.

摘要翻译： 执行规定的算术处理的逻辑电路包括解码器，其将一个或多个二进制输入数据转换成恒定汉明权重的第一多个比特数据，而不管输入数据的汉明权重，连接到 解码器，根据接收到根据解码器转换的第一多个比特数据，并且将所接收的第一多个比特数据的比特位置替换，改变第一多个比特数据的比特模式并生成第二多个比特数据 为了规定的算术运算的目的，以及连接到互连网络的编码器，并且将在互连网络中生成的第二多个位数据转换为一个或多个二进制输出数据。

公开(公告)号：US20080215955A1

公开(公告)日：2008-09-04

申请号：US12032872

申请日：2008-02-18

申请人： Daijiro Kimbara ,  Hiroo Nakano ,  Tetsuro Iwamura ,  Atsushi Kobayashi ,  Masahiko Motoyama ,  Hideki Teraoka ,  Atsushi Shimbo ,  Hideo Shimizu

发明人： Daijiro Kimbara ,  Hiroo Nakano ,  Tetsuro Iwamura ,  Atsushi Kobayashi ,  Masahiko Motoyama ,  Hideki Teraoka ,  Atsushi Shimbo ,  Hideo Shimizu

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G06F11/1008

摘要： A semiconductor storage device includes: a memory configured to store data at a first address and store an error detecting code corresponding to the data at a second address which is set up in a predetermined relation with the first address and different from the first address; and an address storage portion configured to store information on address relation between the first address and the second address.

摘要翻译： 半导体存储装置包括：存储器，其被配置为在第一地址处存储数据，并且在与第一地址以预定关系建立并且与第一地址不同的第二地址处存储对应于数据的错误检测码; 以及地址存储部，被配置为存储关于所述第一地址和所述第二地址之间的地址关系的信息。